Traveling Wave Characteristics Based Pilot Protection Scheme for Hybrid Cascaded HVDC Transmission Line

Dalin Mu; Sheng Lin; Xiaopeng Li

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Traveling Wave Characteristics Based Pilot Protection Scheme for Hybrid Cascaded HVDC Transmission Line PDF

- ORCID：
Dalin Mu ¹
✉
- ORCID：
Sheng Lin ¹
✉
- ORCID：
Xiaopeng Li ²
✉

1. School of Electrical Engineering, Southwest Jiaotong University, Chengdu 611756, China； 2. State Grid Sichuan Electric Power Research Institute, Chengdu 610041, China

Updated：2024-05-20

DOI：10.35833/MPCE.2023.000412

OUTLINE

Abstract

The hybrid cascaded high-voltage direct current (HVDC) transmission system has various operation modes, and some operation modes are having sharply increasing requirements for protection rapidity, while the traditional pilot differential protection (PDP) has poor rapidity, and even refuses to operate when faults occur on the DC line. Therefore, a novel pilot protection scheme based on traveling wave characteristics is proposed. First, the adaptability of the traditional PDP applied in engineering is analyzed for different operation modes. Then, the expressions of the forward traveling wave (FTW) and backward traveling wave (BTW) on the rectifier side and the inverter side are derived for different fault locations. From the theoretical derivation, the difference between the BTW and FTW on the rectifier side is less than zero, and the same is true on the inverter side. However, in the event of an external fault of DC line, the difference between the BTW and FTW at near-fault terminal protection installation point is greater than zero. Therefore, by summing over the product of the difference between BTW and FTW of the rectifier side and that of the inverter side, the fault identification criterion is constructed. The simulation results show that the proposed pilot protection scheme can quickly and reliably identify the short-circuit faults of DC line in different operation modes.

Keywords

Hybrid cascaded high-voltage direct current (HVDC) transmission system; DC line; operation mode; pilot protection

I. Introduction

HYBRID cascaded high-voltage direct current (HVDC) systems, which combine the advantages of line commutated converter based HVDC (LCC-HVDC) and modular multilevel converter based HVDC (MMC-HVDC) technologies, have become a hot spot for academic research and engineering applications [

1]-[3]. For example, the Baihetan-Jiangsu HVDC Project of China (referred to as the Bai-Jiang Project) is a hybrid cascaded HVDC project, and has been put into operation in 2022. To ensure the safe and stable operation of the hybrid cascaded HVDC project, the traveling wave protection of the DC lines is equipped as the primary protection [4], [5], and the differential undervoltage protection and pilot protection are equipped as the backup protection [6]-[9]. Among them, the pilot protection configured in the project is generally pilot differential protection (PDP), which has absolute selectivity. However, in order to avoid the influence of the transient process of the ultra-long line capacitive current, a long time delay must be carried out, and the operation time of PDP is as long as 1.1 s [10]. The converter valve protection such as the maximum trigger angle monitoring protection will operate before the PDP operation [11], [12]. Unfortunately, the PDP loses the role of backup protection for the DC line.

To improve the rapidity of PDP, extensive studies have been carried out from the aspects of PDP optimization [

10], [13]-[15] and new protection principles [16]-[27]. In terms of the PDP optimization, with regard to the problem of HVDC systems blocking caused by improper coordination of the PDP and the maximum trigger angle monitoring protection, the PDP blocking logic with a delay of 600 ms is removed, and the time combination of PDP and converter valve protection is optimized in [10]. The AC voltage is used as an auxiliary criterion for PDP in [13], which can provide selectivity for the delay blocking logic, and the proposed optimization method considers the reliability and rapidity of PDP.

In terms of new principles of pilot protection, it mainly includes the protection schemes based on different feature quantities at both ends of the DC line, or the protection schemes using boundary characteristics of the DC line. For the former, a PDP principle based on the virtual impedance of the fault component is proposed in [

16], which can achieve fault identification and high sensitivity for different kinds of faults. In addition, the boundary characteristics are also used. Electrical similarity and cosine distance are also used to identify DC line faults in [17]-[19]. For example, the correlation between the forward traveling wave (FTW) of line-mode fault voltage on the rectifier side and the backward traveling wave (BTW) of line-mode fault voltage on the inverter side are calculated to formulate the detection criterion of DC line fault in [17], but the selection of the threshold value for fault identification cannot be founded. Directional pilot protection method is also used in [20], [21]. However, this method not only requires to send the local protection information to the remote end, but also needs to send the information back from the remote end, resulting in long delay and complex time sequence.

For the latter, the DC line fault of LCC-HVDC is identified by using surge impedance at tuning frequency and transient energy ratio based on the DC filter (DCF) boundaries at both ends of the DC line in [

22], [23]. The proposed method may be affected by the operation state of the DCF. Regarding the smoothing reactor boundary of MMC-HVDC, the voltage polarity and power characteristics of the reactor are used to construct the protection criterion in [25], and the proposed method is simple but has high sensitivity. In addition, a protection method that does not depend on the line boundary is proposed in [27]. The above methods improve the protection performance for the DC line to a certain extent, and shorten the pilot protection operation time from the second level to the 100-ms level.

However, for the hybrid cascaded HVDC systems with a structure similar to the Bai-Jiang Project, the three MMCs on the inverter side adopt a half-bridge submodule, with as many as 621 operation modes [

28]. The boundaries at both ends of the DC line are not symmetrical. There are significant differences in the fault characteristics for DC lines in different operation modes. For example, when the inverter side of the hybrid cascaded HVDC systems operates in half-voltage mode only with MMC, the MMC submodule will discharge after the DC line fault, and the fault development process is rapid due to the small dampness of the system. If the traditional PDP is not applicable to different operation modes of hybrid cascaded HVDC systems, it is necessary to study an accurate and fast pilot protection method for DC lines that takes into account the operation mode.

Based on this, the difference in the rapidity requirements of PDP in different operation modes of hybrid cascaded HVDC systems is considered, and a novel pilot protection scheme, which is suitable for multiple operation modes, is proposed. The principle of PDP adopted in the existing engineering is introduced in detail, which requires long delays to eliminate the effect of line distribution capacitance. The characteristics of line-mode voltage after fault at different positions are analyzed, and the FTW and BTW expressions are derived. Through analysis, it is found that only when the DC line fault occurs, both the difference values between BTW and FTW on the rectifier side and the inverter side are less than zero, but the external fault of DC line does not have such a feature. Therefore, this paper identifies the short-circuit faults of DC lines based on this characteristic. The proposed pilot protection scheme does not need to consider the transient process of faults in AC system, which improves the rapidity of the protection operation.

II. Adaptability Analysis of PDP for DC Lines

A. Hybrid Cascaded HVDC System and Operation Mode

This paper focuses on the Bai-Jiang Project in China, a typical hybrid cascaded HVDC project. The rectifier of the hybrid cascaded HVDC systems is constructed with two 12-pulse LCCs, and the inverter is composed of a 12-pulse LCC in series with three parallel MMCs. Due to the symmetry of the bipolar structure for cascaded HVDC system, this paper only analyzes the unipolar structure, as shown in Fig. 1, where f₁ represents the DC line fault, f₂ represents the backward external fault of DC line, and f₃ represents the forward external fault of DC line.

Fig. 1 Unipolar structure of full-voltage operation.

Hybrid cascaded HVDC systems have two operation modes: full-voltage and half-voltage [

28]. At the same time, the number of MMCs in operation is considered. For the full-voltage operation mode, the inverter side has three operation modes, i.e., an MMC, two MMCs, and three MMCs are put into operation, respectively. For the half-voltage operation mode, the inverter side has four operation modes, i.e., a 12-pulse LCC, an MMC, two MMCs, and three MMCs are put into operation, respectively. The MMC submodule capacitor uncontrollably discharges to the fault point when a short-circuit fault occurs in the DC system. In order to consider the most serious fault conditions for the proposed pilot protection scheme, this paper takes the case where three MMCs are put into operation simultaneously as an example for analysis.

This paper takes the bipolar full-voltage operation (Mode a), the bipolar half-voltage operation of high-voltage valve (Mode b), and the bipolar half-voltage operation of low-voltage valve (Mode c) as examples for fault analysis. The unipolar structures of Mode b and Mode c are shown in Fig. 2.

Fig. 2 Unipolar structures of half-voltage operation. (a) Mode b. (b) Mode c.

Combined with Fig. 1 and Fig. 2, different structures of the converter station will result in different boundary components at both ends of the DC line for Modes a-c. Mode a and Mode b are affected by the single-phase conductivity of the LCC, and the inverter side will not discharge to the fault point when a short-circuit fault occurs on the DC line. However, for Mode c, the MMC will definitely discharge to the fault point when a short-circuit fault occurs on the DC line, and its fault current will have a huge impact on the DC system.

B. Adaptability Analysis of PDP

The difference of the DC line current between the rectifier station and the inverter station $i_{d i f}$ is calculated, and if it is greater than the setting value within a certain period of time, it will be determined that a short-circuit fault occurs on the DC line. The criteria can be expressed as:

\{\begin{array}{l} i_{d i f} = |i_{D L} - i_{D L O S T}| \\ i_{R E S} = |i_{D L} + i_{D L O S T}| / 2 \\ i_{d i f} > m a x (i_{s e t}, k_{s e t} i_{R E S}) \end{array}

(1)

where $i_{D L}$ is the DC line current of the rectifier station; $i_{D L O S T}$ is the contralateral current; $i_{R E S}$ is the restraint current; $i_{s e t}$ is the setting value; and $k_{s e t}$ is the ratio factor.

In the project, to prevent the PDP malfunction resulted from the transient influence of AC short-circuit fault, the following protection logic is formulated: the current differences before and after 65 ms on the rectifier side and the inverter side, i.e., $Δ i_{R}$ and $Δ i_{I}$ , are calculated, respectively. If the current difference $Δ i_{R}$ or $Δ i_{I}$ is greater than the setting value (0.105 p.u.), a 600 ms lock-up delay will be carried out. And if $Δ i_{R}$ or $Δ i_{I}$ still exceeds the setting value during the lock-up period, the 600 ms lock-up delay will be repeated. This is called delay lock-up strategy (DLS). At the same time, after satisfying the PDP criterion, a 500 ms operation delay is required before the signal is issued. Therefore, the PDP requires a delay of 1.1 s.

According to the actual engineering parameters, this paper builds a simulation model based on PSCAD/EMTDC, and analyzes the PDP operation performance in different modes of hybrid cascaded HVDC systems. Figure 3 shows the simulation results of $Δ i_{R}$ and $Δ i_{I}$ , the state of DLS $i_{d i f}$ , and the DC line currents $i_{M M C 1}$ - $i_{M M C 3}$ of MMC1-MMC3, when a 100 $Ω$ grounding fault occurs at the midpoint of the DC line for Mode c. The operation results of the PDP $L_{P D P}$ for inverter and rectifier stations are shown in Fig. 3(e). The control strategy of Mode c on the inverter side is that MMC1 adopts constant DC voltage control, and MMC2 and MMC3 adopt fixed active power control. The control characteristic curves of inverter station MMCs are shown in Fig. 4, where $U_{d c r e f}$ , $P_{m m c 1}$ , $P_{r e f, m m c 2}$ , and $P_{r e f, m m c 3}$ are the reference voltage of MMC1, the active power of MMC1, the reference active power of MMC2, and the reference active power of MMC3, respectively. The fault time is 2 s, and the fault duration time is 1.5 s. The control strategy of MMCs is the same in the full-voltage operation mode and half-voltage operation of low-voltage valve mode.

Fig. 3 PDP operation characteristics of DC line fault for Mode c. (a) $Δ i_{R}$ and state of DLS. (b) $Δ i_{I}$ and state of DLS. (c) $i_{d i f}$ . (d) $i_{M M C}$ . (e) $L_{P D P}$ .

Fig. 4 Control characteristic curves of inverter station MMCs. (a) MMC1. (b) MMC2. (3) MMC3.

It can be observed from Fig. 3 that the last peak time when $Δ i_{R}$ is greater than the setting value 0.105 p.u. appears at 2.024 s, which is the moment that the last DLS is executed, and the PDP will block for 600 ms. The current difference between the rectifier side and the inverter side of the positive line $Δ i_{P d i f}$ increases rapidly and it is greater than the PDP threshold value. Coupled with the protection operation delay of 500 ms, the fastest operation time is 1.124 s after the fault. MMC1 discharges after the fault, and its discharging current $i_{M M C 1}$ can reach 2.86 kA, which is 1.713 times the rated current 1.67 kA, and can exceed 2.4 kA continuously for a long time. MMC1 operates at a high fault current state for a long time. Similarly, $Δ i_{I}$ is greater than the setting value at 2.142 s, and the fastest operation time is 1.242 s after the fault due to the operation of DLS. MMC1 also operates with a longer period for high fault current, which seriously threatens the reliable operation of the system. In addition, the PDP adaptability in the other two modes are also analyzed, and the MMC does not discharge to the fault point. That is, the requirement for the rapidity of pilot protection for Mode c is much more urgent compared with Mode a and Mode b. Therefore, it is urgent to propose a fast pilot protection scheme to reduce the harm of the huge inrush current to the HVDC system in Mode c.

III. Fault Characteristic Analysis

The electrical quantities between the bipolar DC line are decoupled by pole-mode conversion. In addition, considering the frequency variable characteristics of the DC line, this paper analyzes the fault characteristics with the line-mode component. The fault characteristics of Modes a-c are analyzed, but only the fault analytical expression of Mode c is given due to space limitations.

A. DC Line Fault

From Fig. 2(b), it can be observed that when a fault f₁ occurs on the positive DC line at a distance of $x$ km from the rectifier side, the Peterson equivalent diagram of the line-mode fault component on both sides of the DC line is shown in Fig. 5.

Fig. 5 Peterson equivalent diagram of fault $f_{1}$ . (a) Rectifier side. (b) Inverter side.

From Fig. 5, the fault component propagates to points $m$ and $n$ , and the refraction and reflection occur at the impedance discontinuity position. As observed from Fig. 5(a), the circuit equation at point $m$ is obtained as:

- 2 Δ u_{f 1} = Z_{c 1} i_{f m 1} + u_{c} + L_{d c f} C_{d c f} \frac{d^{2} u_{c}}{d t^{2}}

(2)

where $Δ u_{f 1}$ is the voltage amplitude at the fault point; $L_{d c f}$ is the equivalent inductance of DCF; $C_{d c f}$ is the equivalent capacitance of DCF; $u_{c}$ is the terminal voltage of $C_{d c f}$ ; $i_{f m 1}$ is the fault current of DC line; $Z_{c 1}$ is the line-mode wave impedance of the DC line; and the subscript 1 represents the fault $f_{1}$ .

For f₁, the relationship of FTW, BTW, and refracted traveling wave at point $m$ , i.e., $u_{B m 1}$ , $u_{E m 1}$ , and $u_{F m 1}$ , respectively, is expressed as:

u_{E m 1} = u_{F m 1} - u_{B m 1}

(3)

$u_{E m 1}$ can be expressed as:

u_{E m 1} = - Δ u_{f 1} e^{- γ_{1} x}

(4)

where $γ_{1}$ is the the line-mode component of the propagation coefficient.

From Fig. 5(a), the BTW $u_{E m 1}$ propagated from the fault point to point $m$ has the following relationship with the refracted wave $u_{m b}$ as:

- 2 Δ u_{f 1} e^{- γ_{1} x} = Z_{c 1} i_{f m 1} + u_{m b}

(5)

where $u_{m b}$ is the refracted voltage at point $m$ .

Therefore, $u_{B m 1}$ can be expressed as:

u_{B m 1} = u_{m b} + Δ u_{f 1} e^{- γ_{1} x} = - Δ u_{f 1} e^{- γ_{1} x} - Z_{c 1} i_{f m 1}

(6)

$i_{f m 1}$ can be calculated according to Fig. 4(a), and the calculation expression is given as:

i_{f m 1} (s) = \frac{- 2 Δ u_{f 1} [s L_{p} + s L_{d c f} + 1 / (s C_{d c f})]}{s (s L_{p} + Z_{c 1}) [s L_{d c f} + 1 / (s C_{d c f})] + s^{2} L_{p} Z_{c 1}}

(7)

$i_{f m 1}$ can be obtained by the first-order model approximation as:

i_{f m 1} (s) = - 2 Δ u_{f 1} \frac{L_{p}}{s + \frac{Z_{c 1}}{L_{p}}}

(8)

Then, the reverse Laplace transform is performed to obtain $i_{f m 1} (t)$ as:

i_{f m 1} (t) = - 2 Δ u_{f 1} L_{p} e^{- \frac{Z_{c 1}}{L_{p}} t}

(9)

From (4), (6), and (9), $u_{B m 1}$ is expressed as:

u_{B m 1} (t) = 2 Z_{c 1} L_{p} Δ u_{f 1} e^{- γ_{1} x - \frac{Z_{c 1}}{L_{p}} t} - Δ u_{f 1} e^{- γ_{1} x}

(10)

Similarly, for the inverter side, the BTW at point $n$ $u_{E n 1}$ can be obtained as:

u_{E n 1} = - Δ u_{f 1} e^{- γ_{1} (L - x)}

(11)

where $L$ is the whole length of DC line.

The FTW at point $n$ $u_{B n 1}$ is expressed as:

u_{B n 1} (t) = 2 Z_{c 1} L_{p} Δ u_{f 1} e^{- γ_{1} (L - x) - \frac{Z_{c 1}}{L_{p}} t} - Δ u_{f 1} e^{- γ_{1} (L - x)}

(12)

The difference between $u_{E m 1}$ and $u_{B m 1}$ , i.e., $Δ u_{m f 1} (t)$ , is expressed as:

Δ u_{m f 1} (t) = - 2 Z_{c 1} L_{p} Δ u_{f 1} e^{- γ_{1} x - \frac{Z_{c 1}}{L_{p}} t}

(13)

The difference between $u_{E n 1}$ and $u_{B n 1}$ , i.e., $Δ u_{n f 1} (t)$ , is expressed as:

Δ u_{n f 1} (t) = - 2 Z_{c 1} L_{p} Δ u_{f 1} e^{- γ_{1} (L - x) - \frac{Z_{c 1}}{L_{p}} t}

(14)

The product of (13) and (14) $K_{1}$ is expressed as:

K_{1} = 4 Z_{c 1}^{2} L_{p}^{2} Δ u_{f 1}^{2} e^{- γ_{1} L - \frac{2 Z_{c 1}}{L_{p}} t}

(15)

From (15), $K_{1}$ is greater than zero. That is, $Δ u_{m f 1}$ and $Δ u_{n f 1}$ have the same sign.

B. Backward External Fault of DC Line

The Peterson equivalent diagram is shown in Fig. 6 when the short-circuit fault $f_{2}$ occurs. From Fig. 6, the boundaries on both sides of the DC line are asymmetrical. The line boundary on the rectifier side consists of the DCF and smoothing reactor. While on the inverter side, the smoothing reactor and MMC are used as the physical boundary. From Fig. 6(a), the FTW at point $m$ $u_{B m 2}$ can be expressed as:

u_{B m 2} (s) = \frac{- 2 Δ u_{f 2} [s L_{p} + s L_{d c f} + 1 / (s C_{d c f}) + Z_{c 1}]}{s Z_{c 1} (s L_{p} + Z_{c 1}) + s Q [s L_{d c f} + 1 / (s C_{d c f})]}

(16)

Fig. 6 Peterson equivalent diagram of fault $f_{2}$ . (a) Rectifier side. (b) Inverter side.

where $Q = 2 Z_{c 1} + s L_{p}$ ; $Δ u_{f 2}$ is the voltage amplitude for the short-circuit fault $f_{2}$ at fault point; and the subscript 2 represents the fault $f_{2}$ .

$u_{B m 2} (t)$ is calculated by the first-order model approximation as:

u_{B m 2} (t) = \frac{- 2 Δ u_{f 2} Z_{c 1}}{L_{p} + Z_{c 1}^{2} C_{d c f}} e^{- \frac{2 Z_{c 1}}{L_{p} + Z_{c 1}^{2} C_{d c f}} t}

(17)

The BTW at point $m$ $u_{E m 2}$ is zero within the time of 2 $L$ / $v$ ( $v$ is the line-mode wave velocity) after the FTW is detected. The FTW at point $m$ propagates to point $n$ , and the BTW at point $n$ $u_{E n 2}$ is expressed as:

u_{E n 2} = u_{B m 2} (t) e^{- γ_{1} L}

(18)

Referring to (5) and (6), the FTW at point $n$ $u_{B n 2}$ can be obtained as:

u_{B n 2} = u_{E n 2} - i_{f n 2} Z_{c 1}

(19)

The DC line current $i_{f n 2}$ can be calculated as:

i_{f n 2} (s) = \frac{u_{m f 2} (t)}{s L_{p} + Z_{c 1} + s L_{m} + 1 / (s C_{m})}

(20)

where $L_{m}$ is the arm equivalent reactance; and $C_{m}$ is the arm equivalent capacitance of the three parallel MMCs.

$i_{f n 2}$ is calculated by the first-order model approximation as:

i_{f n 2} (s) = - 2 Δ u_{f 2} \frac{Z_{c 1} C_{m} / G}{s + 2 Z_{c 1} / G}

(21)

where $G = L_{p} + 2 Z_{c 1}^{2} C_{m} + Z_{c 1} L_{d c f} (Z_{c 1} + L_{p})$ .

The reverse Laplace transform is performed for (21), and $i_{f n 2} (t)$ can be expressed as:

i_{f n 2} (t) = - \frac{2 Δ u_{f 2} Z_{c 1} C_{m}}{G} e^{- \frac{2 Z_{c 1}}{G} t}

(22)

The expression of $u_{B n 2}$ is given as:

u_{B n 2} (t) = \frac{2 Δ u_{f 2} Z_{c 1}^{2} C_{m}}{G} e^{- \frac{2 Z_{c 1}}{G} t} + u_{m f 2} (t) e^{- γ_{1} L}

(23)

The difference between $u_{E m 2}$ and $u_{B m 2}$ , i.e., $Δ u_{m f 2} (t)$ , is given as:

Δ u_{m f 2} (t) = \frac{2 Δ u_{f 2} Z_{c 1}}{L_{p} + Z_{c 1}^{2} C_{d c f}} e^{- \frac{2 Z_{c 1}}{L_{p} + Z_{c 1}^{2} C_{d c f}} t}

(24)

The difference between $u_{E n 2}$ and $u_{B n 2}$ , i.e., $Δ u_{n f 2} (t)$ , is given as:

Δ u_{n f 2} (t) = - \frac{2 Δ u_{f 2} Z_{c 1}^{2} C_{m}}{G} e^{- \frac{2 Z_{c 1}}{G} t}

(25)

The product of (24) and (25) $K_{2}$ is expressed as:

K_{2} = - \frac{4 Δ u_{f 2}^{2} Z_{c 1}^{3} C_{m}}{G (L_{p} + Z_{c 1}^{2} C_{d c f})} e^{- \frac{2 Z_{c 1}}{L_{p} + Z_{c 1}^{2} C_{d c f}} t - \frac{2 Z_{c 1}}{G} t}

(26)

From (26), $K_{2}$ is less than zero. That is, $Δ u_{m f 2} (t)$ and $Δ u_{n f 2} (t)$ have different signs.

C. Forward External Fault of DC Line

For the fault $f_{3}$ , the Peterson equivalent circuit diagram is shown in Fig. 7. According to Fig. 7(a), the FTW at point $n$ $u_{B n 3}$ can be expressed as:

u_{B n 3} (s) = \frac{- 2 Δ u_{f 3} Z_{c 1}}{s (2 Z_{c 1} + s L_{p})}

(27)

Fig. 7 Peterson equivalent diagram of fault $f_{3}$ . (a) Rectifier side. (b) Inverter side.

where $Δ u_{f 3}$ is the voltage amplitude for the short-circuit fault $f_{3}$ at fault point; and the subscript 3 represents the fault $f_{3}$ .

$u_{B n 3} (t)$ is obtained by the reverse Laplace transform as:

u_{B n 3} (t) = - 2 Δ u_{f 3} e^{- \frac{2 Z_{c 1}}{L_{p}} t}

(28)

However, the BTW is zero within the time 2 $L$ / $v$ after the FTW being detected at point $n$ . The FTW at point $n$ propagates to $m$ on the full line length of $L$ , and the BTW at point $m$ $u_{E m 3}$ is expressed as:

u_{E m 3} = - 2 Δ u_{f 3} e^{- \frac{2 Z_{c 1}}{L_{p}} t - γ_{1} L}

(29)

The FTW at point $m$ $u_{B m 3}$ can be obtained as:

u_{B m 3} = u_{E m 3} - Z_{c 1} i_{f m 3}

(30)

The DC line current $i_{f m 3}$ can be calculated as:

i_{f m 3} (s) = \frac{u_{E m 3} [s L_{p} + s L_{d c f} + 1 / (s C_{d c f})]}{[s L_{d c f} + 1 / (s C_{d c f})] (Z_{c 1} + s L_{p}) + s L_{p} Z_{c 1}}

(31)

$i_{f m 3}$ is expressed by the first-order approximation model as:

i_{f m 3} (s) = 2 u_{E m 3} \frac{1 / L_{p}}{s + 2 Z_{c 1} / L_{p}}

(32)

The reverse Laplace transform is performed for the above equation, and $i_{f m 3} (t)$ is expressed as:

i_{f m 3} (t) = \frac{2 u_{E m 3}}{L_{p}} e^{- \frac{2 Z_{c 1}}{L_{p}} t}

(33)

The expression of $u_{B m 3}$ is given as:

u_{B m 3} (t) = 4 Δ u_{f 3} \frac{Z_{c 1}}{L_{p}} e^{- γ_{1} L - \frac{4 Z_{c 1}}{L_{p}} t} - 2 Δ u_{f 3} e^{- γ_{1} L - \frac{2 Z_{c 1}}{L_{p}} t}

(34)

The difference between $u_{E m 3} (t)$ and $u_{B m 3} (t)$ , i.e., $Δ u_{m f 3} (t)$ , is given as:

Δ u_{m f 3} (t) = - 4 Δ u_{f 3} \frac{Z_{c 1}}{L_{p}} e^{- γ_{1} L - \frac{4 Z_{c 1}}{L_{p}} t}

(35)

The difference between $u_{E n 3} (t)$ and $u_{B n 3} (t)$ , i.e., $Δ u_{n f 3} (t)$ , is given as:

Δ u_{n f 3} (t) = 2 Δ u_{f 3} e^{- \frac{2 Z_{c 1}}{L_{p}} t}

(36)

The product of (35) and (36) $K_{3}$ is expressed as:

K_{3} = - 8 Δ u_{f 3}^{2} \frac{Z_{c 1}}{L_{p}} e^{- γ_{1} L - \frac{6 Z_{c 1}}{L_{p}} t}

(37)

From (37), $K_{3}$ is less than zero. That is, $Δ u_{m f 3} (t)$ and $Δ u_{n f 3} (t)$ have different signs.

Similarly, Mode a and Mode b are also analyzed, and the above regularities still hold true. That is, the products of the traveling wave difference for the rectifier side and the inverter side are all greater than 0 for all of the three kinds of operation modes when short-circuit faults occur on the DC line, and it is less than 0 in the cases of external faults. In addition, since Mode b operates in the same way as the traditional LCC-HVDC structure, it shows that the proposed pilot protection scheme is also suitable for the traditional LCC-HVDC system.

IV. Pilot Protection Scheme

A. Start-up Criterion

The start-up criterion is carried out by the change of the line-mode current. The improved current gradient algorithm is used, and the expression is shown as:

I_{s t a r t} = {\sum_{N = i + 1}^{i + 3} i}_{1} (N) - {\sum_{N = i - 3}^{i - 1} i}_{1} (N) > Δ i_{s e t}

(38)

where $i_{1} (N)$ is the line-mode current sampling value on the rectifier or inverter side of the DC line; and $Δ i_{s e t}$ is the setting value, and it is 0.01 p.u..

B. Fault Identification Criterion

From the analysis in Section III, it can be observed that when short-circuit faults occur on the DC line, both the difference between BTW and FTW on the rectifier side and that on the inverter side have the same sign. For the external fault, they have different signs. Therefore, based on the data of the FTW and BTW of the first detection of the traveling wave after the fault, the product of $Δ u_{m f} (n)$ and $Δ u_{n f} (n)$ is calculated, and if it is greater than 0, the DC line fault is identified. The pilot protection criterion of DC line fault is set as:

K = \sum_{n = 0}^{P} Δ u_{m f} (n) Δ u_{n f} (n) > 0

(39)

where $P$ is the number of sampling points, and the value of $P$ is determined by the sampling data window. Theoretically, the shorter the length of the data window, the faster the fault detection, which satisfies the protection rapidity requirements, but the protection reliability may be reduced by the influence of system disturbance. The longer the data window, the longer the fault detection time, which meets the protection reliability requirements, but reduces the protection operation quickness. Based on this, the time window of the traveling wave difference is taken as 0.2 ms in this paper. Therefore, $P$ is equal to 20.

The DC line fault is identified when $K > 0$ . Otherwise, it indicates that the external fault of the DC line occurs.

C. Fault Pole Identification Criterion

For a short-circuit fault on the DC line, in order to further determine whether the fault is located on the positive line, negative line, or bipolar line, the zero-mode component of fault voltage $u_{0}$ is used to construct the fault pole identification criterion, and the expression is given as:

\{\begin{array}{l} u_{0} \geq u_{0 s e t} & N P \\ u_{0} \leq - u_{0 s e t} & P P \\ - u_{0 s e t} < u_{0} < u_{0 s e t} & D P \end{array}

(40)

where $u_{0 s e t}$ is the protection threshold value, which is set to be greater than the maximum unbalance voltage of the bipolar fault, and it can be set to be 0.05 p.u.; $N P$ represents that the short-circuit faults on the negative line; $P P$ represents that the short-circuit faults on the positive line; and $D P$ represents that the short-circuit faults on the bipolar line.

D. Flowchart of Pilot Protection Scheme

The flowchart of the proposed pilot protection scheme of the DC line for the hybrid cascaded HVDC system is shown in Fig. 8. The voltage and current on the rectifier side and the inverter side of the bipolar DC line are measured. The line-mode current and voltage and the zero-mode voltage are calculated using the measured data. The FTW and BTW can also be calculated. When the start-up criterion is met, the traveling wave difference on the rectifier side and the inverter side are calculated, respectively. The product K is calculated and used to determine whether the criterion is satisfied. If $K > 0$ , it indicates that a short-circuit fault occurs on the DC line, and the fault pole is further identified. Otherwise, it is determined that no fault occurs on the DC line.

Fig. 8 Flowchart of proposed pilot protection scheme.

V. Simulation Validations

A. Simulation Model and Control Strategy

Bipolar models in different operation modes of the hybrid cascaded HVDC systems are built on PSCAD/EMTDC as follows.

1) Model a. The rectifier station adopts two 12-pulse LCCs, the high-voltage side of the inverter station is a 12-pulse LCC, and the low-voltage side includes three parallel MMCs, of which the number of modules on MMC bridge arm is 200. The control strategy is that the rectifier side adopts fixed DC current control, the high-voltage side of the inverter side adopts fixed DC voltage control, the low-voltage side of inverter station adopts fixed DC voltage control and fixed reactive power control, and the remaining two MMCs adopt fixed active power control and fixed reactive power control.

2) Mode b. Rectifier side and inverter side both have a 12-pulse LCC in operation. The rectifier side adopts fixed DC current control, and the inverter side adopts fixed DC voltage control.

3) Mode c. Rectifier side has a 12-pulse LCC, and inverter side contains three parallel MMCs. The control strategy of the rectifier side is the same as that of Mode b, and the control strategy of the three MMCs is the same as that of Mode a. The DC line adopts the frequency variable parameter model and the line length $L$ is 2086 km. The sampling frequency is 100 kHz.

B. Performance Verification of Proposed Pilot Protection Scheme

In the three operation modes, the following two cases are simulated.

Case 1: 100 $Ω$ grounding short-circuit fault $f_{1}$ occurs at x=1000 km.

Case 2: metal grounding short-circuit fault $f_{3}$ occurs on the positive DC line.

For the fault $f_{1}$ , the simulation results of the FTWs and BTWs on the rectifier and inverter sides, i.e., $u_{B m 1}$ , $u_{E m 1}$ and $u_{B n 1}$ , $u_{E n 1}$ , respectively, and $Δ u_{m f 1}$ and $Δ u_{n f 1}$ are shown in Fig. 9. For the fault $f_{3}$ , the simulation results are shown in Fig. 10.

Fig. 9 Simulation results of FTW and BTW at $m$ and $n$ for fault $f_{1}$ . (a) Mode a. (b) Mode b. (c) Mode c.

Fig. 10 Simulation results of FTW and BTW at $m$ and $n$ for fault $f_{3}$ . (a) Mode a. (b) Mode b. (c) Mode c.

It can be observed from Fig. 9 that, after the short-circuit faults occur on the DC line, the FTWs and BTWs on the rectifier and inverter side completely overlap within a short period when the fault traveling wave is detected. Subsequently, the FTWs on both sides begin to decrease and then increase, that is, the FTWs begin to change in the opposite direction. However, the BTWs still remain unchanged in the original direction, and the BTWs basically stabilize rapidly in Mode a and Mode b. For Mode c, the BTW on the rectifier side increases and decreases, while the BTW on the inverter side slowly increases, and the value of Mode c is closer to that of Mode a. The main reason for this difference is that the capacitors of three MMCs will discharge in Mode c. It can be observed from Fig. 10 that for fault $f_{3}$ , the FTW on the inverter side is almost zero, and only the BTW can be detected within the time 2 $L$ / $v$ after the FTW is obtained. From Section III-C, $Δ u_{n f 3}$ is less than zero, and $Δ u_{m f 3}$ is greater than zero. According to (39), $K < 0$ , which indicates that the DC line is not faulty.

As can be observed from Figs. 9 and 10, the identification of the fault location can be completed within 0.2 ms after the fault traveling wave is detected, respectively, on the rectifier side and inverter side. In addition, for DC line double terminal protection, the time of data calculation and transmission cannot be ignored. The time spent on data transmission and calculation is within 20 ms. Therefore, the fault detection time is only 20.2 ms, which is a significant improvement over the 100 ms of many improved pilot protection schemes.

C. Adaptability of Pilot Protection to Diverse Fault Conditions

The working conditions of fault locations, transition resistors, and fault types are considered in three modes to verify the adaptability of the proposed pilot protection scheme. The identification results are shown in Table I, where “A” means an internal fault, “B” means an external fault, “P” means a positive line fault, “N” means a negative line fault, and “DP” means a bipolar line fault.

Table I Simulation Results of Proposed Pilot Protection Scheme

Operation mode	Fault case	$R_{f}$ ( $Ω$ )	$K$	Result
Mode a	$f_{1}$ -P-500	300	$> 0$	A/P
	$f_{1}$ -P-1500	300	$> 0$	A/P
	$f_{1}$ -P-2000	300	$> 0$	A/P
	$f_{1}$ -N-1500	300	$> 0$	A/N
	$f_{1}$ -P-500	500	$> 0$	A/P
	$f_{1}$ -P-1500	500	$> 0$	A/P
	$f_{1}$ -P-2000	500	$> 0$	A/P
	$f_{1}$ -D-1000	0	$> 0$	A/DP
	$f_{2} - P$	0	$< 0$	B/P
Mode b	$f_{1}$ -P-500	300	$> 0$	A/P
	$f_{1}$ -P-1500	300	$> 0$	A/P
	$f_{1}$ -P-2000	300	$> 0$	A/P
	$f_{1}$ -N-1500	300	$> 0$	A/N
	$f_{1}$ -P-500	500	$> 0$	A/P
	$f_{1}$ -P-1500	500	$> 0$	A/P
	$f_{1}$ -P-2000	500	$> 0$	A/P
	$f_{1}$ -D-1000	0	$> 0$	A/DP
	$f_{2} - P$	0	$< 0$	B/P
Mode c	$f_{1}$ -P-500	300	$> 0$	A/P
	$f_{1}$ -P-1500	300	$> 0$	A/P
	$f_{1}$ -P-2000	300	$> 0$	A/P
	$f_{1}$ -N-1500	300	$> 0$	A/N
	$f_{1}$ -P-500	500	$> 0$	A/P
	$f_{1}$ -P-1500	500	$> 0$	A/P
	$f_{1}$ -P-2000	500	$> 0$	A/P
	$f_{1}$ -D-1000	0	$> 0$	A/DP
	$f_{2} - P$	0	$< 0$	B/P

Note: taking f₁-P-500 as an example, it indicates a positive line fault at x=500 km for fault f₁.

D. Comparison with Existing Schemes

From the Table I, $K$ is always greater than zero for different cases of $f_{1}$ , and the DC line fault can be identified. $K$ is less than zero for fault $f_{2}$ . In the three modes, the proposed pilot protection scheme can accurately and reliably identify DC line faults.

E. Influence of Noise

In actual engineering, the influence of noise is inevitable. It is necessary to study the performance of pilot protection under noise interference. In particular, the noise is mixed in the first step during the measurement of electrical quantities. Therefore, Gaussian white noise is added to the voltage and current signals with signal-to-noise ratios (SNRs) of 30 dB and 40 dB. The positive line fault at $x = 500$ km for three operation modes with 1000 $Ω$ fault resistance is simulated to demonstrate the robustness performance. The results are shown in Table II. Obviously, the proposed pilot protection scheme can still detect faults with noise at 30 dB and 40 dB, and it has a high anti-noise ability.

Table II Results of Proposed Pilot Protection Scheme with Different SNRs

SNR (dB)	Operation mode	x (km)	$K$	Result
30	Mode a	500	$>$ 0	A/P
	Mode b	500	$>$ 0	A/P
	Mode c	500	$>$ 0	A/P
40	Mode a	500	$>$ 0	A/P
	Mode b	500	$>$ 0	A/P
	Mode c	500	$>$ 0	A/P

F. Comparison with Existing Schemes

Some pilot protection schemes have been proposed using double terminal components [

17], [22], [25], [26]. The comparative results of the proposed pilot protection scheme and the existing pilot protection schemes in terms of the maximum detected fault transition resistance and the maximum fault detection time are presented in Table III. As can be seen in Table III, compared with the existing pilot protection schemes, the proposed pilot protection scheme takes a shorter time in the fault detection of the DC line. At the same time, it is also capable of detecting pole-to-ground faults with a high resistance of 1000

Ω

Table III Comparison Results of Proposed Pilot Protection Scheme with Existing Ones

Pilot protection scheme	The maximum fault resistance (Ω)	Sampling time window (ms)
[17]	Not declared	65.0
[22]	300	0.5
[25]	1000	5.0
[26]	400	10.0
Proposed	1000	0.2

VI. Conclusion

The hybrid cascaded HVDC system has various operation modes, and there are significant differences in the characteristics of DC line faults in different operation modes. Affected by the diverse types of converters, the fault current in some operation modes increases rapidly, and the requirement for protection rapidity is very high. For exemple, the discharge current of MMC on the inverter side is up to 1.7 times as that during normal operation in some modes, which poses a great threat to the safe operation of the system. Therefore, it means that the traditional PDP with a time delay of 1.1 s is no longer applicable. Based on this, this paper proposes a fast pilot protection scheme applicable to multiple operation modes according to the product of the difference voltages between the BTW and FTW on the rectifier side and the difference voltages between the BTW and FTW on the inverter side. This scheme does not require long time delays to eliminate the effect of line distributed capacitance discharge, which meets the requirements of protection rapidity. The simulation results further verify the performance of the proposed pilot protection scheme.

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