Journal of Modern Power Systems and Clean Energy

ISSN 2196-5625 CN 32-1884/TK

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Calculation Method for Commutation Failure Fault Level in LCC-HVDC System Under Single-line-to-ground Faults Considering DC Current Variation  PDF

  • Renlong Zhu
  • Xiaoping Zhou
  • Hanhang Yin
  • Lerong Hong
  • An Luo
  • Yandong Chen
  • Hanting Peng
the College of Electrical and Information Engineering, Hunan University, Changsha 410082, China; the School of Electrical and Information Engineering, Changsha University of Science and Technology, Changsha 410114, China

Updated:2023-11-15

DOI:10.35833/MPCE.2022.000724

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Abstract

Earlier studies have reported some calculation methods for commutation failure fault level (CFFL) in line-commutated-converter based high-voltage direct current (LCC-HVDC) system under single-line-to-ground (SLG) faults. The accuracy of earlier methods is limited because they only consider the commutating voltage drop and phase shift, while neglecting the DC current variation. Hence, this paper proposes a CFFL calculation method under SLG faults considering DC current variation, for better planning and designing of LCC-HVDC systems. First, the fault commutating voltage magnitude and phase shift are calculated. Then, the fault DC voltage during different commutation processes is deduced. Based on the commutating voltage magnitude and phase shift, and DC voltage during different commutation processes under SLG faults, the characteristics of CFFL with different fault time are demonstrated and analyzed. Next, the transient time-domain response of the DC current after the fault is obtained based on the DC transmission line model. Discrete commutation processes are constructed based on the commutation voltage-time area rule to solve the extinction angle under different fault levels and fault time. Finally, the CFFL is calculated considering the fault time, commutating voltage drop, phase shift, and DC current variation. The accuracy of the proposed method compared with the traditional method is validated based on the CIGRE benchmark model in PSCAD/EMTDC.

I. Introduction

THE line-commutated-convert-based high-voltage direct current (LCC-HVDC) system is widely used for bulk power transmission between load center and energy resources due to its large transmission capacity, low power losses, and low cost [

1]-[3]. The commutation failure (CF) may cause a short-term interruption of DC power, which leads to the power imbalance and temporary overvoltage in the AC system [4], [5].

The mechanism and influencing factors of CF have been thoroughly investigated over the past decades. Reference [

6] defines the voltage-time area for the first time, and then studies the influencing factors of CF, such as DC current, commutation reactance, and voltage drop based on the quasi-state equation. Reference [7] proposes commutation failure immunity index (CFII) to depict the immunity of inverters to CF. However, the simulation method based on PSCAD/EMTDC is time-consuming and lacks mechanistic and physical explanations for CF. Thus, the analytical approaches for CF risk calculation are motivated. CFII is further used to assess local and concurrent CFs theoretically [8]-[10]. The analytical approaches in [7]-[10] focus on symmetrical three-phase-to-ground (TPG) faults and ignore the DC current variation. For TPG faults, [11]-[13] further investigate critical commutating voltage or CFII by considering the DC current variation. However, the CFII under single-line-to-ground (SLG) faults is not fully studied. Since SLG faults are the most common ones in the AC system, it is worthwhile to investigate the CF mechanism and characteristic under SLG faults. Moreover, this work will better benefit the planning and designing of the LCC-HVDC system. For SLG faults, [14] calculates the commutating voltage based on the quasi-state equation of LCC-HVDC and power flow equation of AC/DC system, and then calculates the commutation failure fault level (CFFL) based on the quasi-state equation of extinction angle and constant DC current. Reference [15] constructs commutation process (CP) considering different fault time, and then calculates the CF probability on the assumption that the DC current remains unchanged and the voltage drop of fault phase is known. Unlike [14] and [15], [16] calculates the commutating voltage drop and phase shift based on the sequence component decomposition of the LCC-HVDC system, providing a more solid base to calculate CFFL rather than calculating CF probability with a presumed voltage reduction. Moreover, all the references neglect the DC current variation after SLG faults, leading to a conspicuous error in CFFL calculation.

In this paper, a CFFL calculation method for LCC-HVDC under SLG faults considering the DC current variation is proposed. Firstly, the commutating voltage drop and phase shift are calculated by using sequence component decomposition of the LCC-HVDC system. Then, the DC voltage during different CPs is deduced, and the transient time-domain response of DC current after fault is obtained. The CF characteristic under SLG faults is further elaborated based on simulation results. Finally, the discrete CPs are constructed, and then the extinction angle under different fault levels and fault time is solved to determine the CF occurrence.

This paper is organized as follows. In Section II, based on the commutating voltage calculation and the DC voltage calculation after fault, the characteristic of CFFL under SLG faults is analyzed. Then, Section III describes the proposed method for CFFL calculation. In Section IV, lots of simulations on the CIGRE benchmark HVDC model are carried out to verify the effectiveness of the proposed method. Finally, Section V concludes this paper.

II. Characteristic of CFFL Under SLG Faults

For a 12-pulse converter used in LCC-HVDC, there are 12 CPs in one cycle T. The CPs and the corresponding commutating voltage are shown in Appendix A Fig. A1, where CPi (i=1,2,) is the discrete CP in order, starting from the one commutated by UcaD around 1.5 s in the CIGRE benchmark model.

Assuming that an SLG fault occurs in phase a, the commutating voltage amplitude and phase shift can be calculated by decomposing the inverter-side AC system into positive-, negative-, and zero-sequence components [

16] as:

UacY=Eeq323x2+3y2-23y+1UbaY=Eeq323x2+3y2+23y+1UcbY=Eeq3 (1)
UacD=Eeq32x2+y2-23y+3UbaD=Eeq3x2+3y2UcbD=Eeq32x2+y2+23y+3 (2)
ΔφacY=arctan3x+3y-33x-3y+1ΔφbaY=arctan-3x+3y+33x+3y+1ΔφcbY=0 (3)
ΔφacD=arctan3x+y-3x-3y+3ΔφbaD=arctanyxΔφcbD=arctan-3x+y+3x+3y+3 (4)

where Uj and Δφj (j=acY, baY, cbY, acD, baD, cbD, ...) are the commutating voltage magnitude and phase shift corresponded in Appendix A Table AI, respectively; Eeq is the equivalent voltage looking into the AC grid from inverter buses; and x=ReZ0+3Zf2Z1+Z0+3Zf, y=ImZ0+3Zf2Z1+Z0+3Zf, Zf is the fault impedance, Z0 and Z1 are the zero- and positive-sequence equivalent impedances looking into the AC grid from inverter buses, respectively. In this paper, the fault impedance is assumed to be fault resistance Rf.

Based on (1)-(4), the relationships between fault resistance and commutating voltage magnitude U and phase shift Δφ during different CPs, i.e., Uj,CPi and Δφj,CPi, are shown in Fig. 1 and Fig. 2, respectively. The commutating voltage magnitude and phase shift of CPi+6 are equal to those of CPi.

Fig. 1  Commutating voltage magnitude during different CPs.

Fig. 2  Commutating voltage phase shift during different CPs.

Considering that the DC voltage is also affected by faults, the fault DC voltage during different CPs needs to be further calculated.

For example, during CP10, the DC voltage of inverter at Y/Y transformer-side UdY can be calculated as the average value during the T/6 starting from the beginning of CP10.

UdY=1π/3αα+60°ucaY(t)d(ωt)-αα+μubaY(t)2d(ωt) (5)

where ucaY(t) and ubaY(t) are the commutating voltages; α is the firing angle; ω is the angular frequency; and μ is the overlap angle.

During CP10, we have:

ubaY(t)=ubY(t)-uaY(t)=2LdiV3D(t)dt (6)

where L is the equivalent commutation inductance; uaY(t) and ubY(t) are the voltages of phases a and b, respectively; and iV3D(t) is the valve current.

Substituting (6) into (5), together with the boundary condition of CP, the DC voltage of the inverter at Y/Y transformer-side can be calculated as:

UdY=62πUcaYcosγ-6πXTIId (7)

where γ is the extinction angle; and XTI=ωL is the equivalent commutation reactance.

During this T/6 period, the DC voltage variation during CP can be expressed by the DC current Id in (7), and the DC voltage variation during the non-CP can be expressed by the AC voltage UcaY in (7). Considering the DC voltage of the inverter at Y/Y transformer-side and Y/D transformer-side together, the DC voltage of the inverter UdI can be calculated as:

UdI=UdY+UdD (8)

The detailed AC voltage during non-CP is shown in Appendix A Fig. A1 and Table AI. Taking CP1 for example, the AC voltage is UabY when UdY is calculated, and the AC voltage is UcbD when UdD is calculated. Based on (8), the DC voltages during different CPs UdI,CPi are shown in Fig. 3.

Fig. 3  DC voltages during different CPs.

The quasi-state equation of extinction angle is expressed as:

γ=arccos2XTIIdU-cosα-Δφ (9)

As shown in (9), the extinction angle calculation should consider the DC current as well as the commutating voltage magnitude and phase shift. Neglecting the DC current variation, as in the traditional method, will lead to a significant error in extinction angle calculation, resulting in a conservative value for the calculated CFFL.

Numerous simulations under different fault levels and fault time are carried out, and the CPs with the first CF are recorded, as shown in Fig. 4. In Fig. 4, the upper CP1-CP6 show the start and end of each CP under normal condition and the color blocks tagged with CP1-CP12 show the CPs with the first CF.

Fig. 4  Relationship of CP with first CF and fault time by simulation results.

As can be observed from Figs. 1 to 3, when the fault resistance is larger than 100 Ω, the commutating voltage magnitude ranks in descending order as follows: UacD,CP1>UacY,CP61.0 p.u.> UcbY,CP2>UbaD,CP5>UcbD,CP3>UbaY,CP4.The phase shift of commutating voltage ranks in descending order from leading to lagging as follows: ΔφcbY,CP2=0°>ΔφcbD,CP3>ΔφacD,CP1ΔφbaY,CP4ΔφacY,CP6>ΔφbaD,CP5. The DC voltage ranks in descending order as follows: UdI,CP4UdI,CP5>1.0 p.u.>UdI,CP3>UdI,CP6>UdI,CP2UdI,CP1. Based on the above results and (9), the commutating voltage is the highest during CP1/CP7. Additionally, the phase shift will also increase the extinction angle. Therefore, the CF risk of CP1/CP7 is zero, and the extinction angle of CP1/CP7 will increase rather than decrease due to the lagging phase. As can be observed from Fig. 4, there is always absolutely no CF risk for CP1/CP7 since CP1/CP7 doesn’t exist in Fig. 4. For CP2/CP8, the commutating voltage remains unchanged compared with the pre-fault commutating voltage, resulting in an nearly zero CF risk. CF only occurs when faults are quite severe and result in an intensive DC current rise. For CP3/CP9, the commutating voltage reduction is conspicuous, and the phase shift is nearly zero, leading to a conspicuous CF risk that ranks second among all CPs. For CP4/CP10, the commutating voltage drops deepest, resulting in the highest CF risk. However, since CP3/CP9 occurs before CP4/CP10, the probability of the first CF occurrence in CP3/CP9 is still higher than that of CP4/CP10. For CP5/CP11, the commutating voltage drops slightly compared with CP3/CP9, and the phase shift lags most. Thus, the CF risk of CP5/CP11 still exist and ranks the third. For CP6/CP12, the commutating voltage remains nearly unchanged, and the phase shift is lagging, resulting in zero CF risk, similar to CP1/CP7.

Furthermore, if we only consider the commutating voltage drop and phase shift, the CFFL of a certain CP should remain unchanged when the fault time is before this CP. However, as can be observed from Fig. 4, the CFFL of certain CP changes with the fault time. Therefore, other CF influence factors such as the DC current variation and fault time should be considered.

III. Proposed Method

The discrete CPs are shown in order in Fig. 5, where μi and γi are the overlap angle and extinction angle of CPi, respectively; tf is the fault time; tsi, tei, and toi are the start time of CPi, end time of CPi, and end time of deionization process, respectively; and the end time of CP12 te12 is used as the start of the time axis.

Fig. 5  Schematic diagram of discrete CPs.

A. Calculation of Fault Commutating Voltage, DC Voltage, and DC Current

The fault commutating voltage can be obtained by (1) and (2). The fault DC voltage can be obtained by (8). In addition, the fault DC current needs to be calculated.

The equivalent circuit of DC transmission line is shown in Fig. 6, where Ld is the equivalent inductance of DC transmission line and the smoothing reactor; Rd is the equivalent resistance of DC transmission line; C is the equivalent capacitor of DC transmission line; Ucd is the voltage of the equivalent capacitor; and the subscripts R and I represent the rectifier-side and inverter-side, respectively.

Fig. 6  Equivalent circuit of DC transmission line.

Considering the DC inductance and the DC capacitor, the inverter-side DC current response in frequency domain and time domain can be calculated as:

IdI(s)=Id(s)=s2C2LdRIdR(0-)X1+CUdR-CUcd(0-)s2C2X1X2-1+s(CX1Ucd(0-)-C2X1UdI+CLdIIdI(0-))s2C2X1X2-1IdI(t)=Id(t)=fId1(t)|IdI(0-),IdR(0-),Ucd(0-) (10)

where X1=sLdR+RdR+1sC; X2=sLdI+RdI+1sC; Ucd(0-) is the voltage of the equivalent capacitor before the fault; IdI(0-) and IdR(0-) are the DC currents before the fault; UdR is assumed to be unchanged; and fId1(t) is the time-domain DC current calculated by the mathematic inversion based on the frequency-domain DC current. Similarly, the capacitor voltage can be calculated as well.

Due to different fault time, the DC current time response can be rewritten as:

Id1(t)=IdN                 t<tffId1(t-tf)    ttf (11)

where IdN is the rated DC current.

B. Construction and Calculation of CP

Once the fault commutating voltage and DC current response have been calculated, we can construct discrete CPs based on voltage-time area rule to solve the corresponding extinction angle.

When tfts1, the fault occurs before CP1 start, and the supply voltage-time area of CP1 can be calculated as:

Asu,CP1=UcaD(cos(α1)-cos(α1+μ1)) (12)

where α1 is the firing angle of CP1.

When ts1<tf<te1, the fault occurs during CP1, and the supply voltage-time area of CP1 can be divided into pre- and after-fault parts, and can be calculated as:

Asu,CP1=UcN(cos(α1)-cos(α1+ω(tf-ts1)))+UcaD(cos(α1+ω(tf-ts1))-cos(α1+μ1)) (13)

where UcN is the rated commutating voltage.

Similarly, when the fault time is during CPi, the supply voltage-time area of CPi is determined by the rated commutating voltage and the fault commutating voltage.

Meanwhile, the demand voltage-time area of CP1 can be calculated as:

Ade,CP1=XTIId1(ts1)+Id10.01μ1180 (14)

In the traditional method, the DC currents at the start and end time of CP1 in (14) remain the rated DC current IdN.

The overlap angle of CP1 μ1 can be solved by making the transcend equation of (12) or (13) equal to (14). Then, γ1 can be calculated as:

γ1=180°-α1-μ1-Δφ1 (15)

where Δφ1 is the phase shift of CP1, i.e., ΔφcaD.

Similarly, we can also construct and calculate CP2. Based on the DC current IdI(30/180×0.01-) and the capacitor voltage Ucd(30/180×0.01-) at the beginning of CP2, the time-domain DC current after CP2 starts can be recalculated as:

Id2(t)=fId2(t)IdI30180×0.01-,IdR30180×0.01-,Ucd30180×0.01- (16)

To lessen the calculation burden, IdR can be assumed as IdI. Similarly, the capacitor voltage can be calculated as well.

The supply voltage-time of CP2 Asu,CP2 can be calculated as:

Asu,CP2=UcbY(cos(α1)-cos(α1+μ2)) (17)

Meanwhile, the demand voltage-time area of CP2 can be calculated as:

Ade,CP2=XTIId2(0)+Id20.01μ2180 (18)

Similarly, in the traditional method, the DC currents at the start and end time of CP1 in (18) remain the rated DC current IdN.

The overlap angle of CP2 μ2 can be solved by making the transcend equation of (16) equal to (18). Then, the extinction angle of CP2 can be calculated as:

γ2=180-α1-μ2+Δφ2 (19)

where Δφ2 is the phase shift of CP2, i.e., ΔφcbY.

The extinction angle of subsequent CPs can also be calculated, similar to (17)-(19), and then compared with the minimum extinction angle γmin to determine the occurrence of CF. Furthermore, considering the effect of constant extinction angle controller after the fault, we assume that there is no CF risk after 6 CPs. If the fault time is around CP3, CP9 and the following CPs have zero CF risk.

The flowchart of the proposed method and traditional method is shown in Fig. 7.

Fig. 7  Flowchart of proposed method and traditional method.

The DC current variation calculation, which is enclosed in the red dotted line, is not included in the traditional method. Initially, the fault time and the initial value of the fault resistance Rf0, which is larger than the actual critical fault resistance, are input into the proposed method. Then, the fault commutating voltage magnitude and phase shift, as well as the fault DC voltage, are calculated. The transient DC current is then calculated. The supply voltage-time area and demand voltage-time area are calculated to determine the extinction angle of CP1. If the calculated extinction angle is less than the minimum extinction angle, the fault resistance is recorded as the critical fault resistance. If the calculated extinction angle is greater than the minimum extinction angle, the extinction angle of CP2 and subsequent CPs are calculated and compared with the minimum extinction angle, as described above. If the calculated extinction angle of CP6 γ6 is still greater than the minimum extinction angle, it indicates no CF risk at this fault level. The value of Rf is then decreased for the next round of calculation until the occurrence of CF, which means the calculated extinction angle should be less than the minimum extinction angle.

IV. Simulation and Results

A. Test Model

To validate the effectiveness of the proposed method, lots of simulations have been performed in the CIGRE benchmark HVDC model based on the PSCAD/EMTDC. The simulation step is 10 μs.

B. Simulation and Calculation Results

Figure 8 shows the relevant waveforms under SLG fault with fault resistance Rf=150 Ω. The fault is applied at phase A when tf=1.500 s with a duration of 0.1 s. The CFFL of this situation is about 152 Ω, which means no CF occurrence if the fault resistance is greater than 152 Ω.

Fig. 8  Simulation waveforms under SLG fault. (a) DC current. (b) Extinction angle. (c) Firing angle. (d) Valve current of Y/D transformer.

As shown in Fig. 8(a), the accuracy of the DC current calculation method in Section III-A is acceptable. In Fig. 8(b), due to the highest commutating voltage among all CPs and the lagging phase shift, the extinction angle of CP1 increases instead of decreasing. As for CP2, although the commutating voltage magnitude and phase shift basically remain unchanged, the DC current rise still enlarges the demand voltage-time area, leading to a decrease in extinction angle. As for CP3, the commutating voltage decreases significantly, forcing CP3 to extend for inductance current shift. Therefore, the extinction angle of CP3 is less than the minimum extinction angle, causing CF occurrence. Additionally, as observed from Fig. 8(c), the firing angle of CP3 remains unchanged because the extinction angle of CP1 is increasing, rendering the constant extinction angle controller unresponsive.

Using the same simulation parameters, the CFFL calculated by the proposed method and the traditional method is around 163 Ω and 84 Ω, respectively. The improved accuracy of the proposed method is mainly attributed to the DC current variation calculation.

To better evaluate both the proposed method and the traditional method, lots of calculations and simulations are performed with varying fault initiation time tf from 1.500 s to 1.510 s, with a step size of 0.01×1/180 s. The simulation results are presented in Fig. 4, while the calculation results of the traditional method and the proposed method are shown in Figs. 9 and 10, respectively.

Fig. 9  Calculation results of traditional method.

Fig. 10  Calculation results of proposed method.

As can be observed from Fig. 9, the CFFL of CP3 or CP4 remains unchanged when the fault time is before CP3 or CP4.

However, when the fault time is during CP3 or CP4, the proportion of voltage-time area supplied by the fault commutating voltage decreases as the fault time passes, resulting in a smaller proportion of after-fault supply voltage-time area in (13). Therefore, CF only occurs with more severe faults as the fault time approaches the end of CP3 or CP4. Moreover, the calculation error of CFFL using the traditional method is noticeable, with an error of 45% at 1.500 s. The results of traditional method are always smaller than the simulation results because the traditional method neglects the increment of DC current.

As shown in Fig. 10, it is evident that the results of the proposed method, which considers the DC current rise, are more accurate than those of the traditional method. For example, the error at 1.500 s is only 7.3%, which is significantly lower than that of the traditional method. When the fault time is between CP1 and CP3, the CFFL of CP3 and CP4 is decreasing. This is because the DC voltage of CP1 and CP2 is dropping after the fault and the DC current increases more when the fault time is far from CP3 and CP4, resulting in a larger demand voltage-time area and a smaller extinction angle. When the fault time is set between CP4 and CP6, the CFFL of CP9 hardly changes because the DC voltage of CP4 and CP5 remains stable after the fault, resulting in similar DC current response characteristics whenever the fault time is around CP4, CP6, or between CP4 and CP6. Nevertheless, the error of the proposed method cannot be ignored at certain fault time since other CF influence factors such as harmonic voltage, LCC-HVDC control system, and dynamic interaction between AC and DC systems are neglected.

To better compare the accuracy of the traditional method and the proposed method, we have calculated the following indices: mean absolute error (MAE), mean absolute percentage error (MAPE), and root mean squared error (RMSE). MAE is a measure of the average distance between simulation results and calculation results. MAPE is a relative measure that scales MAE to be in percentage units. RMSE is the standard deviation of the residuals. The calculations of these indices are shown in (20)-(22), respectively.

MAE=1ni=1nRfs-Rfc (20)
MAPE=1ni=1nRfs-RfcRfs (21)
RMSE=1ni=1n(Rfs-Rfc)2 (22)

where Rfs and Rfc are the simulation and calculation results, respectively.

The smaller the values of MAE, MAPE, and RMSE are, the more accurate the calculation method is. The indices are shown in Table I.

TABLE I  Comparation of Proposed Method and Traditional Method
MethodMAE (Ω)MAPE (p.u.)RMSE (Ω)
Traditional 82.57 0.473 91.43
Proposed 50.16 0.287 66.70

As shown in Table I, the proposed method is more accurate than the traditional method because all three indices of the proposed method are smaller than those of the traditional method.

V. Conclusion

In this paper, a CFFL calculation method that considers DC current variation in LCC-HVDC system under SLG faults is proposed. The proposed method is validated with lots of simulation results from the CIGRE benchmark model built in PSCAD/EMTDC, and it can be concluded as follows.

1) The proposed method achieves greater accuracy in calculating CFFL under SLG faults than the traditional method, due to the consideration of DC current variation.

2) However, the proposed method still exhibits noticeable errors under certain conditions. Further investigation is required to account for the impact of factors such as harmonic voltage, LCC-HVDC control system, and dynamic interaction between AC and DC systems when calculating CFFL.

Appendix

Appendix A

In Fig. A1, iVn is the current flowing through valve n Vn (n=1,2,,6); and the subscripts D and Y represent the variables at Y/D and Y/Y transformers, respectively.

Fig. A1  CPs demonstration. (a) Twelve-pulse converter at inverter side. (b) CPs in order.

TABLE AI  Commutating Voltage of Different CPs

Commutation

process

TransformerCommuting voltageDC voltage (before CP)
V1D-V3D (CP11) Y/D UbaD UcaD
V3D-V5D (CP3) UcbD UabD
V5D-V1D (CP7) UacD UbcD
V2D-V4D (CP1) UcaD UcbD
V4D-V6D (CP5) UabD UacD
V6D-V2D (CP9) UbcD UbaD
V1Y-V3Y (CP10) Y/Y UbaY UcaY
V3Y-V5Y (CP2) UcbY UabY
V5Y-V1Y (CP6) UacY UbcY
V2Y-V4Y (CP12) UcaY UcbY
V4Y-V6Y (CP4) UabY UacY
V6Y-V2Y (CP8) UbcY UbaY

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