Abstract
The series line-commutated converter (LCC) and modular multilevel converter (MMC) hybrid high-voltage direct current (HVDC) system provides a more economical and flexible alternative for ultra-HVDC (UHVDC) transmission, which is the so-called Baihetan-Jiangsu HVDC (BJ-HVDC) project of China. In one LCC and two MMCs (1+2) operation mode, the sub-module (SM) capacitors suffer the most rigorous overvoltage induced by three-phase-to-ground fault at grid-side MMC and valve-side single-phase-to-ground fault in internal MMC. In order to suppress such huge overvoltage, this paper demonstrates a novel alternative by employing the MMC-based embedded battery energy storage system (MMC-BESS). Firstly, the inducements of SM overvoltage are analyzed. Then, coordinated with MMC-BESS, new fault ride-through (FRT) strategies are proposed to suppress the overvoltage and improve the FRT capability. Finally, several simulation scenarios are carried out on PSCAD/EMTDC. The overvoltage suppression is verified against auxiliary device used in the BJ-HVDC project in a monopolar BJ-HVDC system. Further, the proposed FRT strategies are validated in the southern Jiangsu power grid of China based on the planning data in the summer of 2025. Simulation results show that the MMC-BESS and proposed FRT strategies could effectively suppress the overvoltage and improve the FRT capability.
TO fulfill the ever-growing energy demand, high-voltage direct current (HVDC) transmission technology has played an essential role in long-distance and bulk-capacity power transmission occasions [
LCC-based HVDC (LCC-HVDC) has been applied in most of practical HVDC projects, due to its high-technology maturity, low-investment cost, and sufficient practical experience. However, the LCC-HVDC introduces some inherent drawbacks such as excessive consumption of reactive power and the incapability to connect weak AC systems. Besides, with the wide application of LCC-HVDC, multi-infeed HVDC frame has been gradually formed in the China East and Guangdong power grid, leading to several serious problems [
In order to make full use of the superiorities of both LCC and MMC, the hybrid HVDC technology has been paid increasing attention to the future power transmission [

Fig. 1 Basic topology of BJ-HVDC.
It should be noted that, the four AC systems at the inverter are accessed with varying degrees of electrical coupling, rather than the ideal dispersion. The AC grid-side fault, which may occur at any inverter-side converter, will occur in the decrease of all AC voltages in varying degrees simultaneously. Then, the inverter LCCs may suffer the CF, and the MMC power delivery is also impeded. The rectifier LCCs are disenable to respond rapidly due to the time delay, e.g., communication delay and trigger delay, resulting in vast power surplus at the inverter. Consequently, the sub-modules (SMs) in MMCs are compelled to overcharge, and eventually, the SM capacitor voltages may exceed these safety thresholds. Besides, the valve-side single-phase-to-ground (VSPG) fault in internal MMCs also forces severe upper-arm SM overvoltage [
Although some additional fault ride-through (FRT) controls have been proposed to mitigate the SM overvoltage [
Currently, an emerging topic on MMC-based embedded battery energy storage system (MMC-BESS) attracts the interest of both the academic and industrial worlds [
The main contributions are summarized as follows.
1) The mechanisms of the SM overvoltage induced by the VSPG and GTPG faults are thoroughly analyzed.
2) Coordinated with the MMC-BESS, new FRT strategies are proposed to suppress SM overvoltage and improve the FRT capability under different faults.
3) The overvoltage suppression of the MMC-BESS is verified against the CAEC in the monopolar BJ-HVDC system on PSCAD/EMTDC, as shown in
4) The proposed FRT strategies are validated by applying the rectifier-side severe AC fault in the southern Jiangsu power grid of China, where the power grid is benchmarked based on the planning data in the summer of 2025 on PSCAD/EMTDC.
The rest of this paper is organized as follows. Section II describes the structure and control of the BJ-HVDC. The inducements of the SM overvoltage are analyzed in Section III. In Section IV, the overview of MMC-BESS is presented. Coordinated with the MMC-BESS, new FRT strategies are proposed in Section V. In Section VI, the simulation verifications are carried out on PSCAD/EMTDC. Section VII dawns the conclusion.
The basic topology of the BJ-HVDC is shown in
In normal operation mode, the inverter LCC transmits half of the total transmission capacity, and the three MMCs equally share the remaining half, which is the so-called mode. When any MMC exits due to the maintenance or failure, the residual two MMCs will deliver half of the capacity, i.e., mode. In this mode, the BJ-HVDC maintains full-power operation, and the MMC reaches its rated capacity. One LCC and only one MMC on the inverter side ( mode) are not permitted to operate for a long time, since the MMC will suffer severe overcurrent and overvoltage under the inverter-side AC faults. Thus, only the inverter LCC continues operating in half DC voltage mode, improving the reliability and delivery capacity.
The control has been discussed minutely in [
The vector current control is adopted for all MMCs. MMC1 adopts CV control, while both MMC2 and MMC3 adopt constant active power control. In addition, all three MMCs adopt constant reactive power control.
Due to the diverse electrical coupling among the inverter AC systems, the severity of the faults induced by different fault locations is also variational. In other words, the inverter-side AC faults are complicated and troublesome. Thus, this section only analyzes the two most severe faults: VSPG fault in internal MMC and GTPG fault at grid-side MMC. Analyses and conclusions are only carried out for the positive pole but are equivalently applicable to the negative pole.
The classical MMC consists of six arms, and each arm is composed of N HBSMs and an inductor L in series. The arm resistance is equivalent to a resistor R. The transformer is configured with a star/delta (Y/△) connection, and its grid side is arranged with a neutral grounding.
The VSPG fault in internal MMC is usually induced by the insulation failure and flashover of wall bushings, thus, it is normally a permanent fault. For a VSPG fault in internal MMC closes to the valve, the arm currents will immediately increase to intolerable levels. To protect the converter, the insulated gate bipolar transistors (IGBTs) will be rapidly blocked by their internal overcurrent protection. The grid-side AC circuit breakers (ACCBs) will also be tripped after several cycles [

Fig. 2 VSPG fault. (a) Equivalent circuits of blocked MMC1. (b) Valve-side voltage waveform.
It should be emphasized that, due to the symmetry of three phases, the analysis presented for a fault in phase a would also apply to the other two phases.
The VSPG fault creates a new zero voltage potential in the faulty phase a. Due to the △ connection, the magnitudes of the line voltages remain unchanged, and the other two non-fault phase voltages rise to the line voltages. Due to their forward-bias, diodes D1, D3, and D5 will be reverse-biased once the IGBTs are blocked. Moreover, before blocking the converter, the sum of the total voltage of all SM capacitors Urj,sum, e.g., Upc,sum, on each arm is approximately equal to , which is higher compared with the valve-side line voltages. Upon the converter is blocked, diodes , , and will also be reverse-biased, and the voltages of all SM capacitors in the lower arms will remain constant. For the faulty phase a, because of the arm inductor L, D4 will be reverse-biased until the current ina decays to zero. Conversely, due to the free-wheeling effect of diodes and L, D6 and D2 will conduct during every negative half-cycle of and , respectively.
For the faulty phase a, the upper-arm SM capacitors will only be charged by the transient overvoltage of DC terminal and the energy stored in L. For non-fault phases, taking phase c as an example, the upper-arm SM capacitors will be charged as shown in
(1) |

Fig. 3 Post-fault characteristics on upper arm in phase c. (a) Post-fault equivalent circuit on upper arm in phase c. (b) Post-fault valve-side voltage waveform in phase c.
In other words, (1) will be fulfilled only during negative half cycles of , and the capacitors will stop being charged once Upc,sum reaches the maximum value Uc,max, given by [
(2) |
where max() is the peak value of . Neglecting the arm resistor R, max() could be approximated as:
(3) |
where uc is the pre-fault phase voltage of the transformer on the valve side; and Lequ is the equivalent reactance of transformer at the valve side. The HBSM-MMC voltage modulation index m is defined as:
(4) |
Assuming UdcM remains constant under the fault, substitute (3) and (4) into (2), then (2) is rewritten as:
(5) |
Supposing that and , the maximum upper arm SM capacitor voltage will be 1.52UdcM approximately. Considering a 10% ripple during the operation, this value may increase to 1.62UdcM. Such an overvoltage could damage the SMs, as the SMs are normally designed to withstand a 1.5 p.u. voltage [
The above analysis ignores the impact of DC power sent by the rectifier LCCs. As the VSPG fault is normally permanent, the rectifier LCCs need to be forced retard, and MMC2 has to be blocked. Then, the BJ-HVDC system should be shut down for repairing and maintenance. Whereas, the rectifier LCCs are disenable to respond rapidly due to the time delay, which will affect the voltages of upper-arm SM capacitors.
Assuming that the rectifier LCCs take ΔtD to be forced retard, the voltage increment ΔUdc of the upper-arm SM capacitors could be calculated as:
(6) |
where Pdc is the DC power transmitted by the rectifier LCCs; and Pac,IL and Pac,M2 are the active power outputs of the inverter LCC and MMC2, respectively. Due to the slight variation of both DC and AC voltages, Pdc, Pac,IL, and Pac,M2 can be kept near the reference values.
As , (6) is simplified and rewritten as:
(7) |
It could be observed from (7) that, the larger Pdc and the longer ΔtD are, the more serious the overvoltage of the upper-arm SM capacitors will be.
Referred as in [
In normal 1+212 mode, both MMC1 and MMC2 reach their rated capacity, and the theory has no extra capability to absorb the excess power. Once a metal GTPG fault occurs at the grid-side MMC1, extensive power will be accumulated at the inverter, inducing unbearable overvoltage.
Based on the instantaneous power theory, the active power delivery of MMC is calculated as:
(8) |
where Pac,Mi is the active power output of the

Fig. 4 GTPG fault occurring at grid-side MMC1.
In other words, the huge DC power conveyed by the rectifier LCCs is only partially dissipated through the MMC2, resulting in vast power surplus at the inverter. Consequently, the SMs of both MMC1 and MMC2 are compelled to overcharge, and the overvoltage of SM capacitor is derived as:
(9) |
where is the duration of the GTPG fault; is the pre-fault voltage for SM capacitor; C0 is the SM capacitor; is the DC power that the rectifier LCCs transmit to the inverter side during the GTPG fault; and is the active power that MMC2 transmits to AC system during the GTPG fault.
In conclusion, the SM capacitors will suffer an intolerant overvoltage level induced by the VSPG and GTPG faults. The auxiliary energy consumption device is necessary to reliably relieve the overvoltage problem.
In contrast to asymmetrical distribution [

Fig. 5 Structure of HBSM with battery energy storage.
The DC-DC converter operates as a buck converter to charge the battery, or a boost converter to discharge the battery.
(10) |

Fig. 6 Operation modes of MMC-BESS and corresponding power flow. (a) Power flow definition. (b) Idle. (c) Charging. (d) Discharging.
where Pes is the active power output of the BESS; and Pac is the active power output of the MMC-BESS. While all three power flows can be bidirectional, only the positive flows of Pdc and Pac are considered due to limited space.
Under steady-state operation, the BESS does not work, and the MMC-BESS just works similar to the traditional MMC in
The primary objective of BESS is to suppress overvoltage, and the mode is infrequent. Thereby, the rated output power of BESS is designed to be equal to that of MMC in mode for size reduction. This will be evidenced later in Section VI.
The controller of the MMC-BESS is primarily divided into two parts: the main controller and the BESS controller.
The structure of main control is shown in

Fig. 7 Structure of main controller.
Different from the traditional MMC control in which DC voltage reference is usually set as the rated DC voltage, relies on the control mode of the MMC-BESS. For the power-control MMC-BESS, is generated by the DC current PI controller, while it is directly set as the upper command value for the DC voltage control converter. Cooperated with BESS, constant average capacitor voltage (ACV) control is employed to regulate the voltage of SM capacitor near the nominal voltage, or to promote it to recover quickly to the pre-fault value under faults. In addition, the SM capacitor may be inserted into or bypassed from the arm using T1 and T2.
The BESS controller controls DC-DC converter of each SM independently. As depicted in

Fig. 8 Structure of BESS controller.
Coordinated with the MMC-BESS, new FRT strategies are proposed in this section to achieve controllable power support or dissipation in different fault scenarios.
Under steady-state operation, the SM capacitor voltages are only adjusted by the main controller, and the BESS is dormant. When the system suffers a fault, the BESS will be activated.
Since the VSPG fault is a normally permanent fault, upon the fault is detected (about 1.0 ms) and the faulty MMC is blocked. After several times of delay, force retard (FR) is applied by magnifying the firing angle of the rectifier LCCs to a relatively large angle such as 120°. Since only the upper-arm SM capacitors undergo the severe overvoltage, once the maximum voltage of the SM capacitors on any upper arm exceeds the protection threshold , the corresponding upper-arm BESSs will be immediately activated, although all lower-arm BESSs remain dormant. When the DC currents of other sturdy MMCs decline close to zero, the healthy MMCs will also be blocked. After several cycles (typically 60-100 ms), the ACCBs are triggered, and then the entire BJ-HVDC system or at least faulty pole is shut down. Summarily, the controls of the upper-arm BESS in faulty MMC and rectifier LCCs are drawn, as shown in

Fig. 9 Controls of upper-arm BESS in faulty MMC and rectifier LCCs. (a) Outer controller of upper-arm BESS in faulty MMC. (b) Controller of rectifier LCCs.
Due to the saturated transmission capacity in mode, the remaining two MMCs will stomach the severe overvoltage when a terrible GTPG fault occurs at any grid-side MMC. In order to shorten the energy absorption of BESS, the DC power transmitted by rectifier LCCs needs to be reduced by minishing the current reference . All BESSs of both MMCs will rouse when the fault is detected and the maximum voltage of the SM capacitors exceeds the protection threshold.
In mode, the FRT strategy for the GTPG fault at grid-side MMC is illustrated in

Fig. 10 FRT strategy for GTPG fault at grid-side MMC in 1+2 mode. (a) Outer controller of BESS. (b) Controller of rectifier LCCs.
If the fault occurs at the inverter LCC, the excess power can be absorbed almost alone by the BESSs without reducing the reference . Similarly, in mode, depending on about 33% spare delivery capacity of the MMCs, the excess power caused by the fault occuring at any converter could be evacuated by the MMCs and BESSs. Thus, in these cases, only the control in
When the sending-end AC bus suffers a fault, the DC power Pdc is restrained, and the receiving-end AC system sustains a shortage of active power. For the serious sending-end AC fault that the DC voltage at the rectifier LCCs UdcR drops to below UdcM, the DC current Idc will drop to zero rapidly, and Pdc will also decrease to zero. Then, this huge deficiency of active power will cause fluctuations on the receiving-end AC system.
To compensate the lack of power, all BESSs of the MMCs are roused to support the power. The outer controller of the BESS under the AC fault at rectifier is shown in

Fig. 11 Outer controller of BESS under AC fault at rectifier.
When the fault is detected, or the current IdcI drops to below 0.95 p.u., the BESS will quickly switch into power output mode. The power reference relies on the real-time power shortage, which could ensure relatively accurate power compensation. The reference is calculated as:
(11) |
where PdcN,Mi is the rated or steady-state active power of the
Besides, the current references of the power-control MMC-BESSs are varied with IdcI to escape the uneven flowage of the MMC DC current Idc,Mi, or prevent the reverse transmission of the DC-voltage-control MMC-BESS.
When a DC line fault occurs, the voltage at the fault position drops close to zero, resulting in the fault current produced by the rectifier rising rapidly and benefiting from the unidirectional continuity of the inverter LCC. The current promptly drops to zero, and the MMCs do not need to block under DC line fault. Hence, the DC fault is similar to the serious sending-end AC fault with the active power deficit lasting longer (over several hundreds of milliseconds), causing grievous detriment on the receiving-end AC system.
Consequently, the FRT strategy for the DC line fault are also similar to that for the AC fault at rectifier, except that will directly reach its rated value, and quickly minishes to zero. Meanwhile, when IdcR first increases to its threshold value, the FR is utilized to convert the rectifier LCCs into the operating mode of the inverter to quench the fault arc.
Conclusively, the outer controller of the BESS considering FRT strategies is concluded, as shown in

Fig. 12 Outer controller of BESS considering FRT strategies.
In this section, to validate the feasibility and effectiveness of the overvoltage suppression and the FRT improvement for the proposed FRT strategies coordinated with the MMC-BESS, two test systems are implemented on PSCAD/EMTDC. One is a monopolar BJ-HVDC system with only MMC1 and MMC2. The AC systems are imitated with the voltage sources and equivalent impedances listed in [
Type | Item | Rectifier | Inverter |
---|---|---|---|
General parameter | Nominal DC power | 8000 MW | |
Nominal LCC DC voltage | 800 kV | 400 kV | |
Nominal MMC DC voltage | 400 kV | ||
Nominal DC current | 5 kA | ||
Length of DC overhead line | 2172 km | ||
Parameter of MMC unit | Normal active power | 667 MW (1+3 mode)/1000 MW (1+2 mode) | |
Number of SMs on an arm | 200 | ||
Normal voltage of SM capacitor | 2.0 kV | ||
SM capacitance | 16.67 μF | ||
Arm reactance | 25.33 mH | ||
Parameter of LCC transformer | Normal capacity | 1200 MVA | |
Winding voltage (L-L) |
525 kV/ 179.75 kV | 510 kV/161.50 kV | |
Leakage reactance | 0.19 | 0.18 | |
Parameter of MMC transformer | Normal capacity | 1125 MVA | |
Winding voltage (L-L) | 510 kV/210 kV | ||
Leakage reactance | 15% |
The battery bank in each SM is composed of plenty of lithium-ion cells connected in series and parallel, and the first-order resistor-capacitor model is used as its equivalent circuit model [
Type | Item | Value |
---|---|---|
General parameter | Nominal DC voltage | 1.0 kV |
Nominal current | 0.56 kA | |
DC-DC converter inductor | 6 mH | |
DC-DC converter switch frequency | 750 Hz | |
Number of cells in parallel | 56 | |
Number of cells in series | 271 | |
Parameter of battery cell | Normal capacity | 2.35 Ah |
Normal voltage | 3.7 V | |
The maximum continuous discharging current | 10 A | |
Ohmic resistance | 0.061 Ω | |
Polarization resistance | 0.021 Ω | |
Polarization capacitance | 1990 F |
As shown in
Assuming that the battery bank operates at the state of charge (SoC) from 20% to 80%, the maximum time that the BESS can maintain a rated power supply MW is about 256 s, which is calculated as:
(12) |
where SoCmax and SoCmin are the upper and lower limits of the SoC, respectively.
In this subsection, the monopolar BJ-HVDC system in mode is utilized. In order to testify the superiority of the overvoltage suppression, the CAEC device is also involved, whose operation principle is introduced in [

Fig. 13 CAEC device.
Assume that the time delay is approximated as:
(13) |
where is the propagation velocity of the communication; lL is the distance to one station from the other station, which is estimated to the length of DC line; tFD is the time to detect the fault; and tTri is the total trigger delay. It is conservatively presumed that km/ms, and ms. Since the research on the fault detection methods [
Base quantities in this subsection are 800 kV for DC voltage, 5 kA for DC current, 4000 MW for active power delivered by converters, and 2.0 kV for SM capacitor voltage. Simulation results and corresponding analysis are given in the following subsections.
At s, a permanent phase a to ground fault is applied in internal MMC1. Three scenarios are simulated as follows.
1) Scenario A11: the proposed FRT strategy with MMC-BESS. The trigger sequence is referred to as in Section V.
2) Scenario A12: FRT strategy with the CAEC. The trigger sequence is similar to scenario A11, except the CAEC.
3) Scenario A13: only MMC1 blocks without other strategies.
For scenarios A11 and A12, the ACCBs of both MMC1 and MMC2 trip with 5-cycle (100 ms) delay after the fault occurs. In scenarios A12 and A13, all MMCs are classical.
The blocking logic of IGBT is generated by themselves with internal overcurrent fault protection which picks up when the current through any IGBT raises above 2 p.u., i.e., 6 kA in this paper. Thus, tFD for the VSPG fault in internal MMC is short, and only 1 ms is adopted. The response and energy absorption for VSPG fault in internal MMC1 are shown in Figs.

Fig. 14 Response for VSPG fault in internal MMC1. (a) Scenario A11. (b) Scenario A12. (c) Scenario A13.

Fig. 15 Energy absorption for VSPG fault in internal MMC1. (a) MMC. (b) CAEC.
Note that, only the upper-arm SM capacitor voltages for the faulty MMC1 are displayed; rectifier and inverter denote the DC voltages measured at kV DC bus port at the rectifier and inverter, respectively; and LCCI denotes the inverter LCC.
As shown in
Comparing the scenarios A11 and A12, the results of DC voltage, DC current, and active power are similar, whereas the upper-arm SM capacitor in phase c for scenario A12 still withstands about 1.59 p.u. of overvoltage. As shown in
As depicted in
At s, a GTPG fault is applied at the grid-side MMC1, and is cleared after 0.1 s ( s). Fault resistance is . The following three scenarios are simulated.
1) Scenario A21: the proposed FRT strategy with MMC-BESS. As shown in
2) Scenario A22: FRT strategy with the CAEC. As stated in [
3) Scenario A23: no strategies. To analyze the impact of detection time, the detection time of both 1 ms and 5 ms is considered. The responses of the three scenarios for the GTPG fault with different detection time are shown in Figs.

Fig. 16 Response for GTPG fault at grid-side MMC1 with 1-ms detection time. (a) Scenario A21. (b) Scenario A22. (c) Scenario A23.

Fig. 17 Response for GTPG fault at grid-side MMC1 with 5-ms detection time. (a) Scenario A21. (b) scenario A22.

Fig. 18 Energy absorption for GTPG fault at grid-side MMC1 with 1-ms detection time. (a) MMC. (b) CAEC.

Fig. 19 Energy absorption for GTPG fault at grid-side MMC1 with 5-ms detection time. (a) MMC. (b) CAEC.
As shown in Figs.
Figures
Nevertheless, the SM capacitor voltages are only bound to 1.52 p.u., since they could only be suppressed indirectly by dissipating the energy stacked at 400 kV DC bus. Besides, with 5-ms detection time, the fault recovery is longer and more terrible, and the CAEC absorbs more energy, as shown in Figs.
Compared with the performance of the CAEC, once the maximum SM capacitor voltages exceed 1.3 p.u., the MMC-BESSs will be promptly activated to restrain SM capacitor voltages to 1.0 p.u., and the SM capacitor voltage is effectively restrained as the maximum 1.35 p.u.. As depicted in Figs.
In order to effectively reveal the FRT improvement, the southern Jiangsu power grid is benchmarked on PSCAD/ EMTDC. The network structure of the power grid is shown in

Fig. 20 Network structure of southern Jiangsu power grid.
As the receiving-end AC faults have been studied in Section VI-A, only the sending-end GTPG fault and DC line fault are studied in this subsection. In the following subsections, due to the limited space, the generator phase angles of G2, G3, and G5 and the active power flows of branches YS→CF, CSN→SB and ZJG→CY are measured. The arrows define the positive direction of the power flow. The base quantities for per-unitizing are 100 MW for the power flow, 8000 MW for the active power delivered by converters, and others are the same as described before. The power transmitted by converters are the sum of two poles.
A near-end fault on three phases with root meam square voltage dropping to 21% is simulated on the grid side of the rectifier LCCs after achieving steady state. The fault is applied at s and lasts for 0.2 s. Two scenarios are considered as follows.
1) Scenario B11: the proposed FRT strategy with MMC-BESS.
2) Scenario B12: conventional MMCs.
As two poles are symmetrical, only the behaviors of positive pole are exhibited as shown in

Fig. 21 Response for AC fault at rectifier. (a) Scenario B11. (b) Scenario B12.
As indicated in
In this subsection, at s, a pole-to-ground fault with fault resistance of is applied in the middle of the positive overhead DC line. Two scenarios are considered as follows.
1) Scenario B21: the proposed FRT strategy with MMC-BESS.
2) Scenario B22: conventional MMCs.
The DC fault handling strategy has been described in detail as in [
As shown in

Fig. 22 Response for DC line fault. (a) Scenario B21. (b) Scenario B22.
This paper demonstrates a novel alternative by employing the MMC-BESS to suppress serious overvoltage and supply emergency power. Firstly, the inducements of SM overvoltage are analyzed. Then, coordinated with MMC-BESS, new FRT strategies are proposed. Finally, several simulation scenarios are carried out to validate the feasibility and effectiveness. The conclusions are drawn as follows.
1) The analyses on the mechanisms of the SM overvoltage are strongly proven, which are mainly induced by the VSPG in internal MMC and the GTPG at grid-side MMC. Besides, the auxiliary energy consumption device is necessary to reliably relieve the overvoltage.
2) The effectiveness and superiority of the proposed FRT strategies based on MMC-BESS are forcefully validated via several simulation scenarios on PSCAD/EMTDC.
References
A. Kalair, N. Abas, and N. Khan, “Comparative study of HVAC and HVDC transmission systems,” Renewable Sustainable Energy Review, vol. 59, pp. 1653-1675, Jun. 2016. [Baidu Scholar]
P. Zhan, C. Li, J. Wen et al., “Research on hybrid multi-terminal high-voltage DC technology for offshore wind farm integration,” Journal of Modern Power Systems and Clean Energy, vol. 1, no. 1, pp. 34-41, Jul. 2013. [Baidu Scholar]
H. Yang, Z. Cai, X. Li et al., “Assessment of commutation failure in HVDC systems considering spatial-temporal discreteness of AC system faults,” Journal of Modern Power Systems and Clean Energy, vol. 6, no. 5, pp. 1055-1065, Sept. 2018. [Baidu Scholar]
C. Guo, P. Cui, and C. Zhao, “Optimization and configuration of control parameters to enhance small signal stability of hybrid LCC-MMC HVDC system,” Journal of Modern Power Systems and Clean Energy, vol. 10, no. 1, pp. 213-221, Jan. 2022. [Baidu Scholar]
F. Feng, J. Yu, W. Dai et al., “Operational reliability model of hybrid MMC considering multiple time scales and multi-state submodule,” Journal of Modern Power Systems and Clean Energy, vol. 9, no. 3, pp. 648-656, May 2021. [Baidu Scholar]
H. Xiao, K. Sun, J. Pan et al., “Review of hybrid HVDC systems combining line communicated converter and voltage source converter,” International Journal of Electrical Power and Energy Systems, vol. 129, pp. 1-10, Jul. 2021. [Baidu Scholar]
H. Rao, Y. Zhou, C. Zou et al., “Design aspects of hybrid HVDC system,” CSEE Journal of Power and Energy Systems, vol. 7, no. 3, pp. 644-653, May 2021. [Baidu Scholar]
X. Li, Z. Xu, and Z. Zhang, “Enhanced ride-through capability under rectifier-side AC fault for series LCC-MMC hybrid HVDC system,” IEEE Access, vol. 9, pp. 153050-153057, Nov. 2021. [Baidu Scholar]
H. Rao, Y. Zhou, S. Xu et al., “Key technologies of ultra-high voltage hybrid LCC-VSC MTDC systems,” CSEE Journal of Power and Energy Systems, vol. 5, no. 3, pp. 365-373, Sept. 2019. [Baidu Scholar]
H. Xiao, K. Sun, J. Pan et al., “Operation and control of hybrid HVDC system with LCC and full-bridge MMC connected in parallel,” IET Generation Transmission & Distribution, vol. 14. no. 7, pp. 1344-1352, Apr. 2020. [Baidu Scholar]
Z. Xu, S. Wang, and H. Xiao, “Hybrid high-voltage direct current topology with line commutated converter and modular multilevel converter in series connection suitable for bulk power overhead line transmission,” IET Power Electronics, vol. 9, no. 12, pp. 2307-2317, Oct. 2016. [Baidu Scholar]
X. Li, K. Han, C. Fan et al., “Study on main circuit configuration and control modes for a new LCC-MMC hybrid HVDC system,” in Proceedings of 2019 IEEE PES Asia-Pacific Power and Energy Engineering Conference, Macao, China, Dec. 2019, pp. 1-5. [Baidu Scholar]
G. Li, J. Liang, F. Ma et al., “Analysis of single-phase-to-ground faults at the valve-side of HB-MMCs in HVDC systems,” IEEE Transactions on Industrial Electronics, vol. 66, no. 3, pp. 2444-2453, Mar. 2019. [Baidu Scholar]
G. Li, W. Liu, T. Joseph et al., “Double-thyristor based protection for valve-side single-phase-to-ground faults in HB-MMC based bipolar HVDC systems,” IEEE Transactions on Industrial Electronics, vol. 67, no. 7, pp. 5810-5815, Jul. 2020. [Baidu Scholar]
Z. Liu, S. Wang, Z. Chong et al., “Controllable and adaptive energy absorption device for hybrid cascaded UHVDC transmission system,” Proceedings of the CSEE, vol. 41, no. 2, pp. 514-524, Jan. 2021. [Baidu Scholar]
Z. Liu, W. Ma, S. Wang et al., “Schematic design of hybrid cascaded ultra HVDC and its modification in dynamic model experiment,” Power System Technology, vol. 45, no. 3, pp. 1214-1222, Mar. 2021. [Baidu Scholar]
X. Guo, L. Liu, Y. Zhou et al., “Overvoltage mitigation control strategies of MMC converter in a hybrid LCC-MMC HVDC system,” Journal of Global Energy Interconnection, vol. 3, no. 4, pp. 412-419, Jul. 2020. [Baidu Scholar]
Z. Zhou, Z. Chen, X. Wang et al., “AC fault ride through control strategy on inverter side of hybrid HVDC transmission systems,” Journal of Modern Power Systems and Clean Energy, vol. 7, no. 5, pp. 1129-1141, Mar. 2019. [Baidu Scholar]
C. Niu, M. Yang, R. Xue et al., “Research on inverter side AC fault ride-through strategy for hybrid cascaded multi-terminal HVDC system,” in Proceedings of IEEE Conference on Energy Internet and Energy System Integration, Wuhan, China, Oct. 2020, pp. 800-805. [Baidu Scholar]
C. Guo, Z. Wu, S. Yang et al., “Overcurrent suppression control for hybrid LCC/VSC cascaded HVDC system based on fuzzy clustering and identification approach,” IEEE Transactions on Power Delivery, vol. 37, no. 3, pp. 1745-1753, Jul. 2021. [Baidu Scholar]
B. Chang, J. Zhou, C. Lin et al., “Hybrid series-connected HVDC system faults analysis,” in Proceedings of 2019
C. Guo, B. Liu, and C. Zhao, “A DC chopper topology to mitigate commutation failure of line commutated converter based high voltage direct current transmission,” Journal of Modern Power Systems and Clean Energy, vol. 8, no. 2, pp. 345-355, Mar. 2020. [Baidu Scholar]
F. Cheng, L. Yao, J. Xu et al., “A new AC fault ride-through strategy for HVDC link with serial connected LCC-VSC hybrid inverter,” CSEE Journal of Power and Energy Systems, vol. 8, no. 1, pp. 175-187, Jan. 2022. [Baidu Scholar]
Y. Yoo, S. Jung, and G. Jang, “Dynamic inertia response support by energy storage system with renewable energy integration substation,” Journal of Modern Power Systems and Clean Energy, vol. 8, no. 2, pp. 260-266, Mar. 2020. [Baidu Scholar]
Y. Xu, Z. Zhang, G. Wang et al., “Modular multilevel converter with embedded energy storage for bidirectional fault isolation,” IEEE Transactions on Power Delivery, vol. 37, no. 1, pp. 105-115, Jan. 2021. [Baidu Scholar]
L. Zhang, H. Peng, Z. Ning et al., “Comparative research on RC equivalent circuit models for lithium-ion batteries of electric vehicles,” Applied Sciences, vol. 7, no. 10, p. 1002, Oct. 2017. [Baidu Scholar]
P. D. Judge and T. C. Green, “Modular multilevel converter with partially rated integrated energy storage suitable for frequency support and ancillary service provision,” IEEE Transactions on Power Delivery, vol. 34, no. 1, pp. 208-219, Feb. 2019. [Baidu Scholar]
Y. Xue, Z. Xu, and Q. Tu, “Modulation and control for a new hybrid cascaded multilevel converter with DC blocking capability,” IEEE Transactions on Power Delivery, vol. 27, no. 4, pp. 2227-2237, Oct. 2012. [Baidu Scholar]
N. Herath, S. Filizadeh, and M. S. Toulabi, “Modeling of a modular multilevel converter with embedded energy storage for electromagnetic transient simulations,” IEEE Transactions on Energy Conversions, vol. 34, no. 4, pp. 2096-2105, Dec. 2019. [Baidu Scholar]
B. Xu, L. Kong, G. Wen et al., “Protection devices in commercial 18650 lithium-ion batteries,” IEEE Access, vol. 9, pp. 66687-66695, Apr. 2021. [Baidu Scholar]
T. Li, Y. Li, and X. Chen, “Fault diagnosis with wavelet packet transform and principal component analysis for multi-terminal hybrid HVDC network,” Journal of Modern Power Systems and Clean Energy, vol. 9, no. 6, pp. 1312-1326, Nov. 2021. [Baidu Scholar]
Q. Zhang, C. Fu, D. Dai et al., “Mechanism analysis and analytical calculation of open line test for HVDC transmission,” Power System Protection and Control, vol. 47, no. 5, pp. 96-105, Mar. 2019. [Baidu Scholar]