Journal of Modern Power Systems and Clean Energy

ISSN 2196-5625 CN 32-1884/TK

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Fault Ride-through Hybrid Controller for MMC-HVDC Transmission System via Switching Control Units Based on Bang-bang Funnel Controller  PDF

  • Yang Liu
  • Zehui Lin
  • Chenying Xu
  • Lei Wang
School of Electric Power Engineering, South China University of Technology, Guangzhou, 510640, China .

Updated:2023-03-24

DOI:10.35833/MPCE.2021.000470

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Abstract

This paper proposes a fault ride-through hybrid controller (FRTHC) for modular multi-level converter based high-voltage direct current (MMC-HVDC) transmission systems. The FRTHC comprises four loops of cascading switching control units (SCUs). Each SCU switches between a bang-bang funnel controller (BBFC) and proportional-integral (PI) control loop according to a state-dependent switching law. The BBFC can utilize the full control capability of each control loop using three-value control signals with the maximum available magnitude. A state-dependent switching law is designed for each SCU to guarantee its structural stability. Simulation studies are conducted to verify the superior fault ride-through capability of the MMC-HVDC transmission system controlled by FRTHC, in comparison to that controlled by a vector controller (VC) and a VC with DC voltage droop control (VDRC).

I. Introduction

MODULAR multi-level converter based high-voltage direct current (MMC-HVDC) is becoming an increasingly attractive solution for long-distance high-voltage power transmission [

1]. Compared with the conventional two-level or three-level converters, each bridge arm of an MMC comprises a number of submodules (SMs) connected in series, which are easy to expand and have a low harmonic distortion rate and switching losses [2]. MMC-HVDC transmission systems are expected to operate robustly under the disturbance of AC power grids and support AC grids in recovering from a severe disturbance. Hence, the fault ride-through capability of MMCs has a significant influence on the stability of the entire power system [3], [4]. Considerable studies have been undertaken to improve the control of MMC-HVDC transmission systems to achieve a better fault ride-through performance.

This study focuses on the MMCs with half-bridge SMs. Owing to its easy implementation and decoupled control of active and reactive power, the vector controller (VC) is widely used for MMC controllers [

5]. A VC can be realized using proportional-integral (PI) controllers or proportional-resonant (PR) controllers. A PI controller has the first-order dynamics and could respond to its input at any frequency [6]. In contrast, a PR controller has the second- or higher-order dynamics and responds to the component of its input at a specific frequency [7]. To enhance the fault ride-through dynamics of MMCs, a DC voltage droop control scheme is implemented in [8]. A PR controller is designed in [9] to suppress the circulating current of an MMC-HVDC transmission system under the grid faults. A systematic tuning guide for the parameters of a dual-loop voltage-controlled MMC is presented in [10], which considers the voltage stability, transient fault current limitation, and stiffness of voltage against load current changes. A parameter optimization approach is proposed for the VC of MMCs in [11] using Monte Carlo simulation. With the optimized parameters, the small-signal stability and dynamic responses of the hybrid AC/DC power system are improved.

The linear controllers [

5]-[11] improve the robustness of MMCs against the grid faults by injecting additional current components with feed-forward control or optimizing controller parameters. These methods are well-developed, and the mature linear analysis tools are available for stability analysis [12]. However, their limitations are not negligible. First, the parameter selection of linear controllers relies on small-signal stability analysis. The mode that shifts away from the equilibrium of the system cannot be considered, which is the situation under the severe grid faults in a power system [13]. Second, the design of linear controllers must consider the tradeoff between the response speed and overshot. Thus, only moderate performance can be achieved in most cases [14]. The maximum control energy of the MMC is sacrificed for robust stability at all the operating points of the power system.

The nonlinear controllers have also been designed to improve the fault ride-through performance of MMC-HVDC transmission systems over the last decade. The output feedback linearization method is employed in [

15] and [16] for the decoupled control of an MMC. Nonlinearities in the model of an MMC can be fully considered in feed-back linearization [15], [16], which improves the robustness and stability of these controllers with respect to external disturbances. A nonlinear phase-unsynchronized power-decoupling control for an MMC is proposed in [17]. By the input-output linearization, the output power of MMC is decoupled without a phase-locked loop (PLL). A real-time optimization-based current reference calculation algorithm is designed in [18] for the MMC operation under the balanced and unbalanced conditions in AC and DC networks. The mathematical optimization-based nonlinear optimal controllers are designed in [19], and the robust control of an MMC is realized with optimized operational costs. Reference [20] employs the exponentials of matrices to discretize the state-space model of an MMC such that a current control law is obtained by pole placement. In [21], a unified numerical method is proposed for calculating the voltages and currents at the DC side of an MMC under fault conditions based on state matrices. Reference [22] proposes a model predictive control to stabilize the MMC system in various operating scenarios by programming the nonlinear properties of MMC into control laws. However, these nonlinear control methods [15]-[22] have a common shortcoming, that is, the control laws of these methods are much more complex than a VC, and the parameter selection is also more difficult. Hence, the nonlinear controllers are not widely employed in practice.

In addition to the above limitations, the existing control methods [

5]-[11], [15]-[22] cannot utilize the full capability of MMC during a fault ride-through event. With the increasing penetration of renewable power generators, there is an urgent need to explore all controllable energy sources in power systems during the transient process. The balance of the power generation and consumption rapidly helps retain the voltage and frequency stability of a power system. Therefore, it is of great importance to explore the full control energy of the MMC at the early stage when a power system recovers from a severe fault. Such investigations have been conducted in our previous study [23], [24], in which bang-bang funnel controllers (BBFCs) are employed for the maximum energy control of voltage-source converters.

In this paper, a fault ride-through hybrid controller (FRTHC) is proposed to improve the fault ride-through performance of MMC-HVDC transmission systems. The highlights of this paper can be summarized as follows. First, a switching control unit (SCU) with a modular structure is proposed, which can be utilized individually or in combination with another SCU in any control loop of the MMC. The application of a BBFC enables the SCU to explore more control energy of the MMC than continuous controllers do. Second, a state-dependent switching law is proposed for the SCU. Based on the switching law, the BBFC and PI control loops of the SCU operate in a switched manner, and the time delays are implemented to guarantee the stable switching between the two controllers. Third, the simulation studies are conducted to investigate the performance of MMC-HVDC transmission systems controlled by FRTHC via electromagnetic and electromechanical transient simulations.

This paper mainly focuses on the control of MMCs under the three-phase metallic AC grid faults. This type of fault is the most serious line-to-ground fault encountered by MMCs, under which the current flowing through the fault point is the largest. This probably leads to a collapse of the voltage and frequency of the entire power system. This paper also considers the fault ride-through control of the MMC-HVDC under the AC asymmetrical fault. The asymmetric fault is another major cause of oscillation or instability in power systems with MMC-HVDC transmission lines.

The remainder of this paper is organized as follows. The model of the MMC-HVDC transmission system is introduced in Section II. In Section III, BBFCs are designed for SCUs in each control loop of FRTHC for rectifier-side and inverter-side MMCs. Section IV presents the switching laws designed for SCUs of an FRTHC system. The results of the simulation and modal analysis are presented in Section V. Based on the results of the simulation and modal analysis, conclusions are presented in Section VI.

II. Model of MMC-HVDC Transmission System

An MMC-HVDC transmission system primarily comprises a rectifier-side MMC, an inverter-side MMC, and their control systems. The schematic of per-phase circuit of an MMC is illustrated in Fig. 1(a), which is a symmetric monopole configuration with the DC bus midpoint O grounded. Each phase leg of the MMC comprises two bridge arms, i.e., an upper arm and a lower arm. Each arm is equipped with N series-connected SMs, which are half-bridge circuits, as illustrated in Fig. 1(b). Each half-bridge SM comprises two insulated gate bipolar transistors (IGBTs) and one DC storage capacitor. In Fig. 1, vc is the capacitor voltage of the SM in the upper or lower arm; vdu and vdl are the DC voltages of the upper and lower arms, respectively; Iu and Il are the currents flowing through the upper and lower arms, respectively; and R1 is the current limiting resistor.

Fig. 1  Schematic of per-phase circuit and SM of an MMC. (a) Per-phase circuit of an MMC. (b) SM structure.

By controlling the on-off states of the IGBTs, each SM works in one of the following three states: inserted, bypassed, and blocked. The desired sinusoidal voltage is synthesized by properly controlling the number of SMs inserted and the voltage output by each SM. The output voltage of each bridge arm is equal to the sum of voltages of all SMs in this arm. The capacitor voltages of the SMs in a bridge arm should be kept close to each other, which is realized by the modulation block in the MMC control. The mainstream modulation methods include multi-level carrier-based and nearest-level modulations.

A schematic of the MMC-HVDC transmission system controlled by VC is illustrated in Fig. 2. The most widely used control configuration of MMCs is VC. In a VC, four parallel control loops are employed for the decoupled control of active power and reactive power related targets of the rectifier-side and inverter-side MMCs. A two-loop structure is adopted in each of the four control loops, i.e., an outer-loop PI controller and an inner-loop PI controller.

Fig. 2  Schematic of MMC-HVDC transmission system controlled by VC.

A. Model of MMC

An MMC connected to node n can be described with its average model as [

25]:

dVd,nξdt=1Cd,n'Id,nξ-Pe,nξSrateVd,nξdIsd,nξdt=2LnEsd,nξ-Vad,nξ-12RnIsd,nξ+12ωsLnIsq,nξdIsq,nξdt=2LnEsq,nξ-Vaq,nξ-12RnIsq,nξ-12ωsLnIsd,nξ (1)

where the subscript n{i, j}, and i and j indicate the nodes i and j, to which the rectifier-side MMC and inverter-side MMC are connected, respectively; the superscript ξ{r,i}, and r and i indicate the variables of the rectifier-side MMC and inverter-side MMC, respectively; Vd,nξ is the pole-to-pole DC bus voltage of the DC bus; Id,nξ is the current of DC line in the MMC-HVDC transmission system, Id,ir=(Vd,ji-Vd,ir)/Rdc, Id,ji=(Vd,ir-Vd,ji)/Rdc, and Rdc is the resistance of DC transmission line of the MMC-HVDC system; Cd,n'=Cd,n+2MC/N, Cd,n is the installed DC bus capacitance, C is the SM capacitance, and M is the number of phases; Pe,nξ is the active power output; Srate is the rated apparent power chosen for the entire power system; Isd,nξ and Isq,nξ are the d- and q-axis output currents, respectively; Rn is the parasitic arm resistance of MMC; Ln is the arm inductance of MMC; Esd,nξ and Esq,nξ are the d- and q-axis output voltages, respectively; Vad,nξ and Vaq,nξ are the d- and q-axis components of AC bus voltage, respectively; and ωs is the synchronous speed of the entire system.

The active and reactive power outputs of the MMC Pe,nξ and Qe,nξ are expressed as:

Pe,nξ=Vad,nξIsd,nξ+Vaq,nξIsq,nξQe,nξ=Vaq,nξIsd,nξ-Vad,nξIsq,nξ (2)

The models describing the dynamics of circulating current, the sum of capacitor voltages, and circulating current controllers are not presented here, which can be found in [

25].

B. Outer-loop Controllers in VC for Rectifier-side MMC

For the rectifier-side MMC, the DC and AC bus voltages are regulated by the outer-loop controllers in a VC, of which the d- and q-axis state equations are expressed as:

dxod,irdt=12Srateαid,iαd,iCd,i'((Vd,ir)2-(Vd,ir*)2)dxoq,irdt=KIoq,i(Va,ir-Va,ir*) (3)

where xod,ir and xoq,ir are the d- and q-axis state variables of outer-loop controllers for the rectifier-side MMC, respectively; αid,i is the bandwidth of the DC bus voltage integrator; αd,i is the bandwidth of the DC bus voltage control loop; the superscript * represent the reference values; and KIoq,i is the integral coefficient of the AC bus voltage controller for the rectifier-side MMC.

The outputs of outer-loop controllers for the rectifier-side MMC are expressed as:

Isd,ir*=xod,ir+12Srateαd,iCd,i'((Vd,ir)2-(Vd,ir*)2)Isq,ir*=xoq,ir+KPoq,i(Va,ir-Va,ir*) (4)

where KPoq,i is the proportional coefficient of the AC bus voltage controller for the rectifier-side MMC.

C. Outer-loop Controllers in VC for Inverter-side MMC

For the inverter-side MMC, the active power output and AC bus voltage are regulated by the outer-loop controllers in a VC, of which the d- and q-axis state equations are expressed as:

dxod,jidt=KIod,j(Pe,ji*-Pe,ji)dxoq,jidt=KIoq,j(Va,ji-Va,ji*) (5)

where xod,ji and xoq,ji are the d- and q-axis state variables of outer-loop controllers for the inverter-side MMC, respectively; and KIod,j and KIoq,j are the integral coefficients of the active power and AC bus voltage controllers for the inverter-side MMC, respectively.

The outputs of outer-loop controllers for the inverter-side MMC are expressed as:

Isd,ji*=xod,ji+KPod,j(Pe,ji*-Pe,ji)Isq,ji*=xoq,ji+KPoq,j(Va,ji-Va,ji*) (6)

where KPod,j and KPoq,j are the proportional coefficients of the active power and AC bus voltage controllers for the inverter-side MMC, respectively.

D. Inner-loop Current Controllers in VC

The inner-loop current controllers in a VC for the rectifier- and inverter-side MMCs share the same structure, so the state equations and outputs of the inner-loop current controllers are similar.

The state equations of inner-loop current controllers can be expressed as:

dxid,nξdt=KIid,n(Isd,nξ*-Isd,nξ)dxiq,nξdt=KIiq,n(Isq,nξ*-Isq,nξ) (7)

where xid,nξ and xiq,nξ are the d- and q-axis state variables of inner-loop current controllers, respectively; and KIid,n and KIiq,n are the d- and q-axis integral coefficients of innner-loop current controllers, respectively.

The outputs of inner-loop current controllers can be expressed as:

Esd,nξ=xid,nξ+Vad,nξ+KPid,n(Isd,nξ*-Isd,nξ)-12ωsLiIsq,nξEsq,nξ=xiq,nξ+Vaq,nξ+KPiq,n(Isq,nξ*-Isq,nξ)+12ωsLiIsd,nξ (8)

where KPid,n and KPiq,n are the d- and q-axis proportional coefficients of the inner-loop current controllers, respectively.

By mimicking the four-loop structure of the VC, an FRTHC is designed and applied for the control of rectifier-side and inverter-side MMCs. A schematic of an FRTHC is illustrated in Fig. 3, in which a four-loop structure is employed for the decoupled control of the active and reactive power of the rectifier-side MMC and inverter-side MMC. Two cascading SCUs are implemented in each of the four control loops. Each SCU operates in a switched manner between a BBFC and PI control loop according to a switching law. In Section III, the operating principle of a BBFC and its applications in the control of different variables of MMCs are introduced.

Fig. 3  Schematic of MMC-HVDC transmission system controlled by FRTHC.

III. BBFC and Its Applications in Control of MMCs

In each control loop of the FRTHC, two cascading SCUs are configured, i.e., an outer-loop SCU and an inner-loop SCU. A BBFC with neutral output is employed in each SCU.

A. BBFC with Neutral Output

BBFC was first proposed in [

26] and designed to regulate the tracking error of the system output with the maximum control energy of controllers, i.e., bang-bang control signals. In this paper, we propose a generalizable bang-bang controller, which may gain the same popularity as PI controllers. As illustrated in Fig. 3, the input and output of each BBFC in the four-loop FRTHC are the same as those of the corresponding PI controller configured at the same location in the VC.

The d-axis frame is aligned to the AC bus voltage vector, which is realized by the phase-locked loop (PLL), so we have Vad,nξ=Va,nξ and Vaq,nξ=0. Therefore, (2) can be rewritten as:

Pe,nξ=Va,nξIsd,nξQe,nξ=-Va,nξIsq,nξ (9)

Hence, the relationship between Pe,nξ and Isd,nξ, as well as Qe,nξ and Isq,nξ, is described with algebraic equations. Moreover, according to the last two differential equations in (1), it can be observed that the relationship between Isd,nξ and Esd,nξ, as well as Isq,nξ and Esqξ, is described with the first-order differential equations. According to the above analysis, the first-order BBFCs can be utilized in SCUs, as shown in Fig. 3.

The control logic of a BBFC with neutral output is expressed as:

q(t)=-1e(t)e+(qold=-1e(t)>0)0   e(t)=0(qold=0e-<e(t)<e+)1   e(t)e-(qold=1e(t)<0) (10)

where q(t) is the output of control logic of the first-order BBFC; e(t)=y*(t)-y(t) is the tracking error of output variable y(t); qold is the value of q(t) at the previous sampling interval; e+ and e- are the upper and lower bounds of the tracking error, respectively; and the symbols and represent the logic operations of “or” and “and”, respectively.

If e(t) and u(t) are negatively correlated, a sufficiently large positive value of u(t) will drive a positive e(t) to be smaller. According to the output of control logic, the control signal generated by the BBFC u(t) is expressed as:

u(t)=U++u0q(t)=-1u0q(t)=0U-+u0q(t)=1 (11)

where u0 is the steady-state value of u(t) at equilibrium; and U+>0 and U-<0 are the positive and negative maximum outputs of the designed BBFC, respectively.

If e(t) and u(t) are positively correlated, a sufficiently large positive value of u(t) drives a positive e(t) to be larger. According to the output of control logic, the control signal generated by the BBFC is expressed as:

u(t)=U++u0q(t)=1u0q(t)=0U-+u0q(t)=-1 (12)

The first-order nonlinear system can be defined as:

y(t)=f(x)+g(x)u(t) (13)

where x is the state vector; and f(x) and g(x) are the piecewise right-continuous functions. If the conditions in (14) are satisfied, e(t) can always be driven into [e-,e+] by the first-order BBFC defined in (10)-(12) [

27].

U++u0>max{-f(x)/g(x)}U-+u0<min{-f(x)/g(x)} (14)

B. BBFCs in SCUs for Rectifier-side MMC and Inverter-side MMC

An outer-loop SCU and an inner-loop SCU connected in a cascading manner are employed for the DC bus voltage control loop of the rectifier-side MMC in the FRTHC. The control logic of the BBFC in the outer-loop SCU for the DC bus voltage control is expressed as:

qvd,ir(t)=-1ΔVd,irevd,ir+(qvd,ir,old=-1ΔVd,ir0)0   ΔVd,ir=0(qvd,ir,old=0evd,ir-<ΔVd,ir<evd,ir+)1   ΔVd,irevd,ir-(qvd,ir,old=1ΔVd,ir0) (15)

where ΔVd,ir=Vd,ir-Vd,ir*; and the subscript vd,i represents the variables in the outer-loop SCU for the DC bus voltage control.

For the inverter-side MMC, two cascading SCUs for controlling its active power output comprise an outer-loop SCU and an inner-loop SCU. The control logic of the BBFC in the outer-loop SCU for the active power control is expressed as:

qpe,ji(t)=-1    ΔPe,jiepe,ji+(qpe,ji,old=-1ΔPe,ji0)0       ΔPe,ji=0(qpe,ji,old=0epe,ji-<ΔPe,ji<epe,ji+)1       ΔPe,jiepe,ji-(qpe,ji,old=1ΔPe,ji0) (16)

where ΔPe,ji=Pe,ji-Pe,ji*; and the subscript pe,j represents the variables in the outer-loop SCU for the active power control.

Because Isd,ir is negatively correlated with ΔVd,ir and Isd,ji is negatively correlated with ΔPe,ji, the outputs of BBFCs in the outer-loop SCU for the DC bus voltage control and active power control share the same form, which can be written as:

Isd,nξ*=Isd,nξ*++Isd,nξ*0qvd,ir(t)=-1 or qpe,ji(t)=-1Isd,nξ*0qvd,ir(t)=0 or qpe,ji(t)=-0Isd,nξ*-+Isd,nξ*0qvd,ir(t)=1 or qpe,ji(t)=1 (17)

where the superscript 0 represents the steady-state value that can be calculated at the equilibrium.

Regarding the BBFCs in the inner-loop SCUs for the DC bus voltage control loop of the rectifier-side MMC and active power control loop of the inverter-side MMC, the control logics can be expressed as:

qisd,nξ(t)=-1     ΔIsd,nξeisd,nξ+(qisd,nξ,old=-1ΔIsd,nξ0)0   ΔIsd,nξ=0(qisd,nξ,old=0eisd,nξ-<ΔIsd,nξ<eisd,nξ+)1   ΔIsd,nξeisd,nξ-(qisd,nξ,old=1ΔIsd,nξ0) (18)

where n{i, j} and the subscripts isd,i and isd,j represent the variables in the inner-loop SCUs for the DC bus voltage control of rectifier-side MMC and active power control of inverter-side MMC, respectively.

Because ΔIsd,nξ=Isd,nξ-Isd,nξ* and Esd,nξ are positively correlated, the outputs of BBFCs in the inner-loop SCUs for the DC bus voltage control and active power control can be expressed as:

Esd,nξ*=Esd,nξ*++Esd,nξ*0qisd,nξ(t)=1Esd,nξ*0qisd,nξ(t)=0Esd,nξ*-+Esd,nξ*0qisd,nξ(t)=-1 (19)

With respect to the AC bus voltage control loops of the rectifier-side MMC and inverter-side MMC in FRTHC, an outer-loop SCU and an inner-loop SCU connected in a cascading manner are utilized as well. The control logics of the BBFCs in the outer-loop SCUs for the AC bus voltage control are expressed as:

qva,nξ(t)=-1    ΔVa,nξeva,nξ+(qva,nξ,old=-1ΔVa,nξ0)0  ΔVa,nξ=0(qva,nξ,old=0eva,nξ-<ΔVa,nξ<eva,nξ+)1  ΔVa,nξeva,nξ-(qva,nξ,old=1ΔVa,nξ0) (20)

where n{i,j} and the subscripts va,i and va,j represent the varibles in the out-loop SCUs for the AC bus voltage control of rectifier-side MMC and inverter-side MMC, respectively.

Because ΔVa,nξ=Va,nξ-Va,nξ* and Isq,nξ are negatively correlated, the outputs of BBFCs in the outer-loop SCUs for the AC bus voltage control can be expressed as:

Isq,nξ*=Isq,nξ*++Isq,nξ*0qva,nξ(t)=-1Isq,nξ*0qva,nξ(t)=0Isq,nξ*-+Isq,nξ*0qva,nξ(t)=1 (21)

The control logics of the BBFC in the inner-loop SCUs for the AC bus voltage control can be expressed as:

qisq,nξ(t)=-1    ΔIsq,nξeisq,nξ+(qisq,nξ,old=-1ΔIsq,nξ0)0  ΔIsq,nξ=0(qisq,nξ,old=0eisq,nξ-<ΔIsq,nξ<eisq,nξ+)1  ΔIsq,nξeisq,nξ-(qisq,nξ,old=1ΔIsq,nξ0) (22)

where the subscript isq,n represents the variables in the inner-loop SCUs for the AC bus voltage control of rectifier-side MMC and inverter-side MMC.

Because ΔIsq,nξ=Isq,nξ-Isq,nξ* and Esq,nξ are positively correlated, the outputs of BBFCs in the inner-loop SCUs for the AC bus voltage control can be expressed as:

Esq,nξ*=Esq,nξ*++Esq,nξ*0qisq,nξ(t)=1Esq,nξ*0qisq,nξ(t)=0Esq,nξ*-+Esq,nξ*0qisq,nξ(t)=-1 (23)

IV. Switching Laws for SCUs of FRTHCs

The switching laws designed for each SCU in the four control loops of the FRTHC offer the following performances. In cases where the magnitude of the tracking error of an output variable overrides a threshold value for a specified length of time, the BBFC in the corresponding control loop is switched on and generates bang-bang control signals. In cases where the magnitude of the tracking error of an output variable remains within a pre-designed interval for a selected length of time, the PI control loop is switched on and generates continuous control signals for asymptotical convergence of the tracking error. To realize the above performance, a state-dependent switching law, as illustrated in Fig. 4, is proposed for each SCU in the FRTHC.

Fig. 4  Schematic of switching law designed for SCUs of FRTHC. (a) Disturbance indicator. (b) Switching signal generator.

The switching law comprises two parts, i.e., a disturbance indicator and switching signal generator. In the disturbance indicator, e represents the absolute value of the tracking error of the control objective y, i.e., Vd,ir, Va,ir, Pe,ji, and Va,ji for outer-loop controllers, and Isd,ir, Isq,ir, Isd,ji, and Isq,ji for inner-loop controllers; τ1y is the threshold value, and it indicates a disturbance occurs when |e| overrides τ1y and it is generally set as half the width of the desired error interval, i.e., τ1y=(e+-e-)/2; Ky is the gain to adjust the triggering speed of the BBFC in an SCU, which is usually selected from 1 to 100 according to the practical situation; and τ2y is generally selected as half of τ1y. The comparator outputs 1 when input A is larger than input B. The clearing port of the integrator inputs C=1 and the integrator output is reset to be 0 when |e| is smaller than τ2y. DBlk denotes the blocking signal of the MMC, and MMC is blocked when DBlk=0. χ=1 indicates that |e|>τ1y lasts longer than γ1y, and γ1y works in a coordinated manner with Ky.

In the switching signal generator, the JK flip-flop module generates Q=1 when a step-up signal of χ is sensed by clearing port C and the initial value of Q is zero. When χ=1, the integrator of the switching signal generator is reset to be 0 and T=1. When χ changes from 1 to 0, the output of the integrator begins to increase. Until the output of the integrator overrides γ2y, T=0. According to the value of T, the control signals generated for the corresponding SCU uscu(t) are expressed as:

uscu(t)=Tubbfc(t)+(1-T)upi(t) (24)

where ubbfc(t) and upi(t) are the outputs of the corresponding PI control loop and BBFC, respectively.

According to the above, the outputs of the SCUs of the FRTHC are expressed as:

Isd,ir*,scu=Tisd,irIsd,ir*,bbfc+(1-Tisd,ir)Isd,ir*,piIsq,ir*,scu=Tisq,irIsq,ir*,bbfc+(1-Tisq,ir)Isq,ir*,piEsd,ir*,scu=Tvd,irEsd,ir*,bbfc+(1-Tvd,ir)Esd,ir*,piEsq,ir*,scu=Tva,irEsq,ir*,bbfc+(1-Tva,ir)Esq,ir*,piIsd,ji*,scu=Tisd,jiIsd,ji*,bbfc+(1-Tisd,ji)Isd,ji*,piIsq,ji*,scu=Tisq,jiIsq,ji*,bbfc+(1-Tisq,ji)Isq,ji*,piEsd,ji*,scu=Tpe,jiEsd,ji*,bbfc+(1-Tpe,ji)Esd,ji*,piEsq,ji*,scu=Tva,jiEsq,ji*,bbfc+(1-Tva,ji)Esq,ji*,pi (25)

where the superscripts “scu”, “bbfc”, and “pi” represent the control signals generated by SCUs, BBFCs, and PI controllers, respectively.

V. Simulation Studies

To test the performance of an MMC-HVDC transmission system controlled by FRTHC, the simulation studies are conducted in a two-machine test power system with PSCAD and a four-machine test power system with MATLAB, respectively.

A. Fault Ride-through Performance of MMC-HVDC Transmission System in Two-machine Test Power System

1) Three-phase-to-ground Fault Occurs at Rectifier-side AC Grid

The layout of a two-machine test power system is illustrated in Fig. 5. A 1000 MVA/640 kV half-bridge-monopolar MMC-HVDC transmission system is connected between two AC grids. The short circuit ratio (SCR) and the parameter X/R of both the rectifier-side and inverter-side AC grids are set as SCR=2.5 and X/R=20, respectively.

Fig. 5  A two-machine test power system with MMC-HVDC transmission system.

The parameters of the MMC-HVDC transmission system are selected as: fn=60 Hz, M=3, N=76, Srate=1000 MVA, Vd*=640 kV, Carm=2800  μF, R=0.005  Ω, and L=50 mH, where Carm is the equivalent arm capacity of MMC. To evaluate the performance of the FRTHC, the simulation results of the test power system controlled by a single VC and a VC with DC voltage droop control (VDRC) are presented for comparison. The voltage droop control can adjust the reference power according to the DC voltage sag in real time, to stabilize DC-side voltage of the MMC [

28]. The tracking error of the active power output of the MMC including the voltage droop control can be expressed as: edroop=Pe,nξ*-Pe,nξ+Kdroopξ(Vd,nξ*-Vd,nξ), where Kdroopξ is the droop coefficient. The parameters of the VC are chosen as: αd=5, αid=4, KPod,1=6, KIod,1=20, KPoq,1=1, KIoq,1=10, KPid,1=0.65, KIid,1=100, KPiq,1=0.65, KIiq,1=100, KPod,2=0.25, KIod,2=5, KPoq,2i=1, KIoq,2=10, KPid,2=0.6, KIid,2=10, KPiq,2=0.6, and KIiq,2=10. These parameters of VC are also adopted for the corresponding PI control loops in SCUs of the FRTHC. The parameters of the droop control are chosen as Kdroopi=0.32 and Kdroopr=0.01.

The parameters of BBFCs and the switching laws of SCUs in the FRTHC of the rectifier-side and inverter-side MMCs are presented in Table I and Table II, respectively.

TABLE I  Parameters of BBFCs and Switching Laws of SCUs in FRTHC of Rectifier-side MMC in Two-machine Test Power System
ParameterDifferent values with different control objectives
Vd,ir loopIsd,ir loopVa,ir loopIsq,ir loop
e+ (p.u.) evd,ir+=0.1 eisd,ir+=0.02 eva,ir+=0.05 eisq,ir+=0.1
e- (p.u.) evd,ir-=-0.1 eisd,ir-=-0.02 eva,ir-=-0.05 eisq,ir-=-0.1
Ky Kvd,ir=70 Kisd,ir=100 Kva,ir=70 Kisq,ir=100
τ1y (p.u.) τ1vd,ir=0.1 τ1isd,ir=0.02 τ1va,ir=0.05 τ1isq,ir=0.1
τ2y (p.u.) τ2vd,ir=0.05 τ2isd,ir=0.01 τ2va,ir=0.03 τ2isq,ir=0.05
γ1y (s) γ1vd,ir=0.18 γ1isd,ir=0.02 γ1va,ir=0.54 γ1isq,ir=0.06
γ2y (s) γ2vd,ir=0.54 γ2isd,ir=0.24 γ2va,ir=0.54 γ2isq,ir=0.24
U+ (p.u.) Isd,ir*+=0.5 Esd,ir*+=1.0 Isq,ir*+=0.5 Esq,ir*+=1.0
U- (p.u.) Isd,ir*-=-0.5 Esd,ir*-=-1.0 Isq,ir*-=-0.5 Esq,ir*-=-1.0
TABLE II  Parameters of BBFCs and Switching Laws of SCUs in FRTHC of Iverter-side MMC in Two-machine Test Power System
ParameterDifferent values with different control objectives
Pe,ji loopIsd,ji loopVa,ji loopIsq,ji loop
e+ (p.u.) epe,ji+=0.2 eisd,ji+=0.04 eva,ji+=0.05 eisq,ji+=0.1
e- (p.u.) epe,ji-=-0.2 eisd,ji-=-0.04 eva,ji-=-0.05 eisq,ji-=-0.1
Ky Kpe,ji=70 Kisd,ji=100 Kva,ji=70 Kisq,ji=100
τ1y (p.u.) τ1pe,ji=0.2 τ1isd,ji=0.04 τ1va,ji=0.05 τ1isq,ji=0.1
τ2y (p.u.) τ2pe,ji=0.1 τ2isd,ji=0.02 τ2va,ji=0.03 τ2isq,ji=0.05
γ1y (s) γ1pe,ji=0.54 γ1isd,ji=0.12 γ1va,ji=0.18 γ1isq,ji=0.18
γ2y (s) γ2pe,ji=0.72 γ2isd,ji=0.24 γ2va,ji=0.18 γ2isq,ji=0.24
U+ (p.u.) Isd,ji*+=-0.1 Esd,ji*+=1.0 Isq,ji*+=0.5 Esq,ji*+=1.5
U- (p.u.) Isd,ji*-=-1.5 Esd,ji*-=-1.0 Isq,ji*-=-0.5 Esq,ji*-=-1.5

The simulation results obtained in the case where a three-phase-to-ground fault occurs at node 1 are illustrated in Fig. 6. The fault is applied at t=2.0 s and cleared at t=2.1 s.

Fig. 6  Fault ride-through performance of MMC-HVDC transmission system controlled by FRTHC, VC, and VDRC under three-phase-to-ground fault. (a) Esdr*. (b) Esqr*. (c) Isdr*. (d) Isqr*. (e) Isdr*-Isdr. (f) Isqr*-Isqr. (g) Vdr*-Vdr. (h) Var-Var*. (i) Esdi*. (j) Esqi*. (k) Isdi*. (l) Isqi*. (m) Isdi*-Isdi. (n) Isqi*-Isqi. (o) Pei*-Pei. (p) Vai-Vai*.

At the rectifier side, both BBFCs in the outer-loop SCUs are triggered and generate bang-bang current reference signals for the inner-loop controllers, as illustrated in by Fig. 6(c) and (d). The current tracking errors are illustrated in Fig. 6(e) and (f). After the d-axis current tracking error overrides the predefined level, the inner-loop BBFC is switched on along the d-axis according to the switching law of the inner-loop SCU. The bang-bang voltage control signals are produced for Esdr*, as shown in Fig. 6(a). The BBFC in the q-axis inner-loop SCU is not triggered, and the q-axis voltage references are illustrated in Fig. 6(b). Owing to the combined effort of the d- and q-axis control voltages, the smaller oscillation and smaller tracking errors are observed in the DC voltage of the rectifier-side MMC, controlled by the FRTHC in comparison to those controlled by VC and VDRC, as illustrated in Fig. 6(g). The voltage dynamics of node 1 with the three control methods are similar, as illustrated in Fig. 6(h).

With respect to the inverter-side MMC, BBFCs in SCUs for the d-axis control loop are triggered, as illustrated by the d-axis reference current in Fig. 6(k) and d-axis control voltage in Fig. 6(i). The bang-bang signals are generated by BBFCs, and the control energy of the MMC is fully utilized. As a result, the tracking errors are smaller observed in the d-axis output current and active power output of the inverter-side MMC controlled by the FRTHC than those controlled by VC and VDRC, as illustrated in Fig. 6(m) and (o), respectively. The BBFCs in SCUs for the q-axis control loop are not triggered, and the references of the q-axis output current and control voltage are generated by PI loops in the SCUs, as illustrated in Fig. 6(l) and (j), respectively. Owing to the combined effort of both the d- and q-axis controllers, the tracking error and oscillation in the output current and AC bus voltage of the inverter-side MMC controlled by the FRTHC are smaller than those controlled by the VC and VDRC, as shown in Fig. 6(n) and (p), respectively. The droop control corrects the tracking error of active power, and the control effect of the VDRC is better than that of the VC. Nevertheless, the VDRC is essentially PI control, and an oscillation phenomenon still exists.

2) Line-to-line Fault Occurs at Inverter-side AC Grid

To further test the performance of the FRTHC in asymmetrical fault events, a line-to-line fault is applied at node 2 at t=2.0 s in the test power system illustrated in Fig. 5. The time of the fault duration is set to be 0.2 s. In this case, the SCR of the inverter-side AC grid is decreased to SCR=1.7, and the SCR of the rectifier-side AC grid is maintained at SCR=2.5. Owing to the asymmetrical fault, MMCs controlled by FRTHC, VC, and VDRC present large tracking errors in the active power output and AC bus voltage, as shown in Fig. 7(o) and (p), respectively. Moreover, the unstable oscillatory modes of VC and VDRC are excited by the fault, where unstable oscillations occur after the fault is cleared at t=2.2 s.

Fig. 7  Fault ride-through performance of MMC-HVDC transmission system controlled by FRTHC, VC, and VDRC under line-to-line fault. (a) Esdr*. (b) Esqr*. (c) Isdr*. (d) Isqr*. (e) Isdr*-Isdr. (f) Isqr*-Isqr. (g) Vdr*-Vdr. (h) Var-Var*. (i) Esdi*. (j) Esqi*. (k) Isdi*. (l) Isqi*. (m) Isdi*-Isdi. (n) Isqi*-Isqi. (o) Pei*-Pei. (p) Vai-Vai*.

At the inverter side, both BBFCs in the outer-loop SCUs are triggered and generate bang-bang current reference signals for the inner-loop controllers, as shown in Fig. 7(k) and (l). The tracking errors of the output currents are illustrated in Fig. 7(m) and (n). As can be observed, both the d- and q-axis currents exhibit unstable oscillatory behaviors in the system controlled by VC and VDRC, respectively. In contrast, the system controlled by the FRTHC does not exhibit any unstable fluctuation. This is mainly because both BBFCs of the inner-loop SCUs in the FRTHC are triggered after the fault occurs, and BBFCs can utilize large control signals at the initial stage of the fault and during the fault recovery process, as illustrated in Fig. 7(i) and (j). Therefore, the oscillatory energy of the system can be dissipated at the early stages of the post-fault process. Consequently, the MMC controlled by the FRTHC does not present unstable oscillations after the PI control loops in the SCUs are switched on.

In terms of the rectifier-side MMC, neither the BBFC in the d-axis outer-loop SCU nor the q-axis outer-loop SCU is switched on during the fault. As shown in Fig. 7(c) and (d), the reference currents are generated by the PI control loops in the outer-loop SCUs throughout the simulated interval. The BBFC of the inner-loop SCU in the d-axis control loop is triggered after the fault occurs, as shown in Fig. 7(a). The BBFC of the inner-loop SCU in the q-axis control loop is not triggered, and the reference of the q-axis control voltage is generated by the PI loop in the SCU, as illustrated in Fig. 7(b). The dynamics of the tracking error of the output currents, denoted by Isdr*-Isdr and Isqr*-Isqr, are illustrated in Fig. 7(e) and (f), respectively. Unstable oscillations are observed in the above current dynamics in the system controlled by VC and VDRC, owing to the impact from the inverter-side MMC.

Unstable oscillations in the active power output of the inverter-side MMC lead to fluctuations in the DC bus voltage Vdi. The current flowing through the DC transmission line oscillates, and the oscillation is transferred to the rectifier-side MMC. Accordingly, unstable oscillations are observed in the DC bus voltage of the rectifier-side MMC controlled by VC and VDRC, as illustrated in Fig. 7(g). The fluctuation of the DC bus voltage results in oscillations in the output currents and power of the MMC. As illustrated in Fig. 7(h), the AC bus voltage exhibits unstable oscillations in the system controlled by VC and VDRC. With the control of a single VC, the test system cannot restore stability oscillates, and finally becomes unstable after the fault is cleared.

B. Fault Ride-through Performance of an MMC-HVDC Transmission System in Four-machine Thirteen-bus Test Power System

The FRTHC is also tested by the control of an MMC-HVDC transmission system in a four-machine thirteen-bus test power system with MATLAB, the schematic of which is shown in Fig. 8.

Fig. 8  A four-machine test power system with MMC-HVDC transmission system.

The parameters of synchronous generators (SGs) and the network can be found in [

29]. The parameters of the MMC-HVDC transmission system are selected as: M=3, N=180,Srate=900 MVA, Vd*=800 kV, Vsmax=400 kV, Ismax=1 kA, L=0.08 p.u., R=0.008 p.u., Carm=9.375 μF, Cd'=100 μF, C=0.0017 F, and Rdc=3.058 Ω. The VC parameters for the MMC-HVDC transmission system are chosen as: αd=50, αid=25, KPod=1, KIod=5, KPoq=1, KIoq=5, KPid=4, KIid=80, KPiq=4, KIiq=80, Ra=20, and αc=200. These parameters are also adopted for the PI control loops in the SCUs of the FRTHC. The parameters of the droop control are chosen as Kdroopi=0.26 and Kdroopr=0.062.

The parameters of the BBFCs and switching laws of SCUs in the FRTHC of the inverter-side MMC and rectifier-side are presented in Table III and Table IV, respectively. The simulation results obtained in the case where a 0.1 s three-phase-to-ground fault occurs at node 2 at t=0.1 s are illustrated in Fig. 9. The control performance of the FRTHC is compared with that of a VC and a VDRC.

TABLE III  Parameters of BBFCs and Switching Laws of SCUs in FRTHC of Rectifier-side MMC in Four-machine Thirteen-bus Test Power System
ParameterDifferent values with different control objectives
Vd,ir loopIsd,ir loopVa,ir loopIsq,ir loop
e+ (p.u.) evd,ir+=0.02 eisd,ir+=0.2 eva,ir+=0.2 eisq,ir+=0.02
e- (p.u.) evd,ir-=-0.02 eisd,ir-=-0.2 eva,ir-=-0.2 eisq,ir-=-0.02
Ky Kvd,ir=1 Kisd,ir=1 Kva,ir=1 Kisq,ir=1
τ1y (p.u.) τ1vd,ir=0.02 τ1isd,ir=0.2 τ1va,ir=0.2 τ1isq,ir=0.02
τ2y (p.u.) τ2vd,ir=0.02 τ2isd,ir=0.2 τ2va,ir=0.2 τ2isq,ir=0.02
γ1y (s) γ1vd,ir=0 γ1isd,ir=0 γ1va,ir=0 γ1isq,ir=0
γ2y (s) γ2vd,ir=0 γ2isd,ir=0 γ2va,ir=0 γ2isq,ir=0
U+ (p.u.) Isd,ir*+=1.0 Esd,ir*+=0.5 Isq,ir*+=1.0 Esq,ir*+=2.0
U- (p.u.) Isd,ir*-=-1.0 Esd,ir*-=-0.5 Isq,ir*-=-1.0 Esq,ir*-=-2.0
TABLE IV  Parameters of BBFCs and Switching Laws of SCUs in FRTHC of Inverter-side MMC in Four-machine Thirteen-bus Test Power System
ParameterDifferent values with different control objectives
Pe,ji loopIsd,ji loopVa,ji loopIsq,ji loop
e+ (p.u.) epe,ji+=0.04 eisd,ji+=0.02 eva,ji+=0.2 eisq,ji+=0.04
e- (p.u.) epe,ji-=-0.04 eisd,ji-=-0.02 eva,ji-=-0.2 eisq,ji-=-0.04
Ky Kpe,ji=1 Kisd,ji=1 Kva,ji=1 Kisq,ji=1
τ1y (p.u.) τ1pe,ji=0.04 τ1isd,ji=0.02 τ1va,ji=0.2 τ1isq,ji=0.04
τ2y (p.u.) τ2pe,ji=0.04 τ2isd,ji=0.02 τ2va,ji=0.2 τ2isq,ji=0.04
γ1y (s) γ1pe,ji=0.001 γ1isd,ji=0.0001 γ1va,ji=0.001 γ1isq,ji=0.001
γ2y (s) γ2pe,ji=0.001 γ2isd,ji=0 γ2va,ji=0 γ2isq,ji=0.005
U+ (p.u.) Isd,ji*+=2.0 Esd,ji*+=0.7 Isq,ji*+=1.0 Esq,ji*+=2.0
U- (p.u.) Isd,ji*-=-1.5 Esd,ji*-=-0.7 Isq,ji*-=-1.0 Esq,ji*-=-2.0

Fig. 9  Dynamics of MMC-HVDC transmission system controlled by FRTHC, VC, and VDRC. (a) Esd,5r*. (b) Esq,5r*. (c) Isd,5r*. (d) Isq,5r*. (e) Vd,5r. (f) Va,5r. (g) Esd,6r*. (h) Esq,6r*. (i) Isd,6r*. (j) Isq,6r*. (k) Vd,6r. (l) Va,6r.

Due to the rectifier-side fault, the BBFCs of the outer-loop SCUs in both the d- and q-axis control loops of the FRTHC for the rectifier-side MMC are switched on. As shown in Fig. 9(c) and (d), the bang-bang current reference signals are generated for the inner-loop controllers. Similarly, BBFCs of the inner-loop SCUs in both the d- and q-axis control loops are triggered. The bang-bang voltage references are generated for the rectifier-side MMC, as illustrated in Fig. 9(a) and (b). Because of the bang-bang signals produced by the FRTHC during the fault, the DC bus voltage and AC bus voltage of the rectifier-side MMC exhibit smaller oscillations and less magnitude deviation than those of the MMC controlled by VC and VDRC, which is illustrated in Fig. 9(e) and (f), respectively.

With respect to the inverter-side MMC, BBFCs in SCUs are triggered in either the d- or q-axis control loop, and all current and voltage references are generated by PI controllers, as illustrated in Fig. 9(g)-(j). Nevertheless, the oscillatory modes are observed in the current and voltage references generated by VC and VDRC, respectively.

In contrast, the MMC controlled by FRTHC does not exhibit any oscillatory behaviour. Consequently, the active power output and AC bus voltage of the inverter-side MMC controlled by the FRTHC exhibit less oscillation and magnitude deviation than those controlled by VC and VDRC, which is verified by Fig. 9(k) and (l), respectively.

The above results demonstrate that the dynamics of the inverter-side MMC are closely related to those of the rectifier-side MMC. Although BBFCs at the inverter side are not switched on, the rectifier-side MMC controlled by FRTHC alleviates the imbalance between the power input and output of the MMC-HVDC transmission system. Therefore, the output variables of MMCs controlled by FRTHC exhibit better performance than those controlled by VC and VDRC. Moreover, the entire test power system is prevented from entering the oscillatory region, and no oscillatory modes are excited when the FRTHC is applied.

C. Modal Analysis of Four-machine Test Power System with MMC-HVDC Transmission Line Controlled by VC

The oscillatory modes of the four-machine thirteen-bus test power system with an MMC-HVDC transmission system controlled by VC are analyzed, and the results are presented in Table III, where v1,g is the state variable of excitation controller of SG g; ωr,g is the speed deviation of the SG g; δg is the power angle deviation of the SG g; and Ψfd,g, Ψ1d,g, Ψ1q,g, and Ψ2q,g are the flux linkages of the field winding, d-axis amortisseur winding, and two q-axis amortisseur windings of the SG g, respectively. There are 42 modes in the transmission system, three of which are unstable. The unstable modes are underlined in Table V.

TABLE V  Oscillatory Modes of Four-machine Thirteen-bus Test Power System with MMC-HVDC Transmission System Controlled by VC
NumberEigenvalue

Frequency

(Hz)

Damping ratioParticipation factorRelevant variableNumberEigenvalue

Frequency

(Hz)

Damping ratioParticipation factorRelevant variable
1 -4185.2 0 1.0000 0.5003 Vd,5r 22 -24.1 0 1.0000 1.1068 xiq,6i
2 -188.8 0 1.0000 1.0712 Isd,6i 23 -14.4 0 1.0000 0.5320 xoq,5r
3 -109.6 0 1.0000 1.3418 Isq,6i 24 3.3 0 -1.0000 0.1819 δ2̲
4 -99.6 0 1.0000 0.9929 v1,4 25 -8.0+j7.0 1.1118 0.7512 0.5378 xid,6i
5 -99.0 0 1.0000 0.5166 v1,2 26 -8.0-j7.0 1.1118 0.7512 0.5378 xid,6i
6 -99.5 0 1.0000 0.5175 v1,1 27 -0.5+j6.8 1.0827 0.0759 0.2598 ωr,1
7 -83.9 0 1.0000 2.5411 Isq,5r 28 -0.5-j6.8 1.0827 0.0759 0.2598 ωr,1
8 -99.4 0 1.0000 0.9788 v1,3 29 -0.5+j7.1 1.1292 0.0681 0.3042 ωr,4
9 -50.3 0 1.0000 1.7514 Isd,5r 30 -0.5-j7.1 1.1292 0.0681 0.3042 ωr,4
10 -15.1+j29.8 4.7425 0.4529 0.7029 xod,5r 31 0.4+j3.8 0.6116 -0.1141 0.2387 δ3̲
11 -15.1-j29.8 4.7425 0.4529 0.7029 xod,5r 32 0.4-j3.8 0.6116 -0.1141 0.2387 δ3̲
12 -29.1+j4.1 0.6570 0.9901 2.4076 xid,5r 33 -4.9 0 1.0000 0.3354 Ψ1q,2
13 -29.1-j4.1 0.6570 0.9901 2.4076 xid,5r 34 -5.0 0 1.0000 0.3627 Ψ1q,3
14 -35.9 0 1.0000 1.2782 Ψ1d,2 35 -3.7+j1.4 0.2274 0.9335 0.1661 Ψ1q,3
15 -36.3+j0.1 0.0086 1.0000 0.3897 Ψ2q,2 36 -3.7-j1.4 0.2274 0.9335 0.1661 Ψ1q,3
16 -36.3-j0.1 0.0086 1.0000 0.3897 Ψ2q,2 37 -3.7 0 1.0000 0.2956 Ψ1q,1
17 -35.5 0 1.0000 0.5889 Ψ1d,4 38 -2.5 0 1.0000 0.3399 xoq,6i
18 -34.2 0 1.0000 0.8650 Ψ1d,1 39 -1.3 0 1.0000 0.8318 Ψfd,1
19 -33.6 0 1.0000 0.5787 Ψ1d,3 40 -1.0 0 1.0000 0.5583 Ψfd,3
20 -30.7 0 1.0000 0.5844 xid,5r 41 -0.8 0 1.0000 0.8127 Ψfd,2
21 -31.2 0 1.0000 0.5606 Ψ2q,1 42 -0.7 0 1.0000 0.6458 Ψfd,4

According to the participation factor of the state variables, the relevant state variables corresponding to the unstable modes are δ2 and δ3. Therefore, it can be observed that the MMC-HVDC transmission system controlled by VC fails to provide sufficient damping for the unstable models in δ2 and δ3. These unstable models result in divergent oscillations in MMCs controlled by VC. Therefore, the results of the modal analysis agree with the simulation results presented in Section V-C.

VI. Conclusion

This paper proposes an FRTHC to improve the fault ride-through capability of MMC-HVDC transmission systems. According to the simulation results, the following conclusions are obtained.

First, the FRTHC is structurally stable, which means that the constant switching between the BBFC and PI control loops does not exist in each SCU. The switching laws are effective, and measurement noise and impulsive disturbances cannot trigger BBFCs. Second, the tracking errors of output variables are smaller in the system controlled by FRTHC. The BBFC of an SCU is able to employ more control energy from the MMC than a PI control loop. This is beneficial for the rapid dissipation of unbalanced energy in the DC capacitors and SM capacitors of MMCs. Along with the rebalance between the power input and output of the MMCs, a stable operation of the entire MMC-HVDC system is guaranteed, and a more satisfactory dynamic performance is obtained by the FRTHC. Third, the FRTHC prevents the MMC-HVDC transmission system from unstable oscillations. The simulation results reveal that the piecewise constant bang-bang control signals generated by BBFCs do not stimulate any oscillatory modes of the test system. Actually, it can be observed that BBFCs help MMC-HVDC suppress the oscillatory modes of SGs and circumvent the poor damping of PI control loops in SCUs.

The SCU built upon the BBFC with neutral output is a highly flexible control unit, and more combinations and variations are expected in the applications of SCUs for the control of various electric facilities. Control energy exploration in power systems with bang-bang control methods is an attractive topic of research, and the wide-area coordination of distributed control energy can be investigated in the future.

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