Superconducting Magnetic Energy Storage Based DC Unified Power Quality Conditioner with Advanced Dual Control for DC-DFIG

Ruohuan Yang; Jianxun Jin; Qian Zhou; Shuai Mu; Ahmed Abu-Siada

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Superconducting Magnetic Energy Storage Based DC Unified Power Quality Conditioner with Advanced Dual Control for DC-DFIG PDF

- ORCID：
Ruohuan Yang (Student Member, IEEE)
✉
- ORCID：
Jianxun Jin (Fellow, IEEE)
✉
- ORCID：
Qian Zhou
✉
- ORCID：
Shuai Mu
✉
- ORCID：
Ahmed Abu-Siada (Senior Member, IEEE)
✉

School of Electrical and Information Engineering, Tianjin University, Tianjin 300072, China .； Department of Electrical and Computer Engineering, Curtin University, Perth, WA 6102, Australia.

Updated：2022-09-24

DOI：10.35833/MPCE.2021.000354

OUTLINE

Abstract

The development of DC custom power protection devices is still in infancy that confines the sensitive loads integrated into medium-voltage (MV) and low-voltage (LV) DC networks. Considering the DC doubly-fed induction generator (DC-DFIG) based wind energy conversion system (WECS), this paper proposes a dual active bridge (DAB) based DC unified power quality conditioner (DC-UPQC) with the integration of superconducting magnetic energy storage (SMES) to maintain the terminal voltage of DC-DFIG and regulate the current flow. The principle of the proposed DC-UPQC has three parts, i.e., parallel-side DAB (PDAB), series-side DAB (SDAB), and SMES, used for the voltage compensation, current and power regulation, and energy storage, respectively. The circuit principle of the PDAB and SDAB and the modeling of SMES are analyzed in this paper. A DC dual control strategy is also proposed to deal with the DC voltage oscillation generated by the AC-side asymmetrical fault. A case study of DC-DFIG interfaced with DC power grid is carried out, integrated with the proposed SMES-based DC-UPQC to verify the high-power applications of the proposed structure. Finally, an experiment is implemented, and the results demonstrate the correctness of the theoretical analysis and the feasibility of the proposed structure.

Keywords

DC network; unified power quality conditioner (UPAC); DC doubly-fed induction generator (DC-DFIG); power quality

I. Introduction

THE medium-voltage (MV) and low-voltage (LV) DC distribution systems have attracted increased attention in the past few years, owing to the advantages of concise structure, high economy, and convenient interface to energy storage devices (ESDs) and renewable power generators (RPGs) [

1], [2]. However, the penetration of power-electronic-controlled DC RPGs will lead to power quality issues [3]. Among DC RPGs, the DC doubly-fed induction generator (DC-DFIG) based wind energy conversion system (WECS) has been widely investigated in [4]-[7], which mainly consists of a DFIG, a diode rectifier, and a rotor-side converter (RSC). Compared with the traditional DFIG, the DC-DFIG-based WECS has a more economical structure since the grid-side converter (GSC) is no longer needed. However, the uncontrolled commutation of the diode rectifier makes the DC-DFIG-based WECS lack the low-voltage ride through (LVRT) capability and thus vulnerable to DC grid faults. What is worse, when an asymmetrical fault occurs at the AC side, there will be a voltage sag accompanied by a 100 Hz voltage oscillation in the DC voltage. If not adequately considered, the voltage oscillation will lead to highly unbalanced current and power, resulting in significant losses of power system revenue and sensitive loads [8], [9].

To improve the LVRT capability of DFIG-WECS, many solutions have been proposed [

10]-[15], which can be approximately classified into two categories, i.e., software-based solutions and hardware-based solutions. Software-based solutions can be further divided into two parts. Some of the software improvements, such as demagnetizing control [10], flux linkage tracking control [11], and current reversely tracking control [12], [13], aim at improving the control strategies of DFIG RSC. When a DC fault occurs, the software-based solutions are still applicable for DC-DFIG, but a concern is raised in [14], [15] that the DC current will rapidly increase with a considerable amplitude in a short time. Such a DC fault current will seriously cause damage to the assailable equipment such as diode rectifier and insulated gate bipolar transistor (IGBT) switches used in DC-DFIG-based WECS.

Some software-based methods are proposed to regulate the DC voltage profile of the DC microgrids, such as hierarchical control, which has been widely investigated. Inside the hierarchical control, the secondary control is responsible for the voltage regulation and current sharing among renewable energy sources [

16], [17]. However, when a severe grid fault occurs, software-based solutions are ineffective in sustaining load voltage due to the limited capacity of the converters. In addition, software modifications lack the capability to protect a certain sensitive load. Therefore, hardware-based solutions should be considered.

Among hardware-based solutions, crowbar protection circuits are the most widely used and have been already commercially adopted in many DFIG-based WECSs [

18], [19]. But the problem of the crowbar protection circuit is that the pulsation of the electromagnetic (EM) torque cannot be confined. Custom power protection devices such as dynamic voltage restorer (DVR) [20], [21], series GSC (SGSC) [22], [23], superconducting fault current limiter-magnetic energy storage (SFCL-MES) [24], and unified power quality conditioner (UPQC) [25]-[27] are proposed for AC DFIG-based WECSs, but they are not suitable for DC-DFIG-based WECSs due to the architectural difference of the two systems. Various types of non-superconducting fault current limiters (FCLs) [28]-[30] and SFCLs [31], [32] also provide good hardware-based solutions, due to their advantages of low cost and straightforward structure. However, several issues should be noted: ① the load voltage cannot be accurately compensated to the rated voltage; ② without the utilization of energy storage, the intermittency of the renewable power sources cannot be well-addressed; ③ various modified controls are not suitable for FCLs, which limit its ability to suppress the voltage and current oscillations.

Relying on the development of the dual active bridge (DAB) [

33]-[35], some DC custom power protection devices have been proposed. Based on the structure, the DC custom power devices (CPDs) can be categorized into two main classifications, i.e., series CPD (SCPD) and parallel CPD (PCPD). PCPDs including various kinds of energy storage interfaced to power grid via power-electronic-based converters [36]-[38], active power filter [39], and power flow controller [40]-[42] provide an additional shunt path to regulate the current quality of the DC transmission line. They can filter the DC current ripple or smooth the time-varying stochastic power caused by the intermittent renewable energy sources. In contrast, SCPDs are utilized to solve the voltage quality issue. The typical SCPDs in DC systems include intelligent uninterruptible power supply (IUPS) [43], DC-DVR or series voltage regulator (SVR) [44], [45], and superconducting magnetic energy storage (SMES) based transformerless SVR (TLSVR) [46]. Although these hardware systems are used for DC voltage restoration, a little concern is raised when the above-mentioned SCPDs are used.

In the field of voltage quality, the DC voltage swell always appears along with the DC voltage sag [

47], [48]. Therefore, the SCPDs are required to have a bidirectional voltage compensation capability. However, the voltage direction of each side of the traditional DC/DC DAB is inherent, which limits the ability to deal with either voltage sag or voltage swell. For instance, the DC-DVR proposed in [44] can only mitigate the voltage sag. To acquire the bidirectional voltage compensation capability, additional converters are required, such as the IUPS proposed in [43] and the SVR proposed in [45], but the increased number of converters will result in a compliable control issue. The AC/AC matrix converter [49] provides a more straightforward structure and a more concise control for bidirectional voltage output. Matrix-converter-based devices are presented in [50]-[52], and their performances in voltage restoration are initially validated in [46].

Combining the advantages of the DAB and matrix converter and synthesizing the functions of PCPD and SCPD, a DAB-based DC-UPQC is proposed in this paper to simultaneously improve the LVRT capability of the DC-DFIG and regulate the output DC current and power. As an ESD for smoothing the time-varying wind power, the SMES is adopted at the DC bus of DC-UPQC. The system configuration of the DC-DFIG-based WECS with the integration of the DAB-based DC-UPQC is shown in Fig. 1. The proposed DC-UPQC comprises three parts: ① a series-side DAB (SDAB) for the voltage regulation, serving as an SCPD; ② a parallel-side DAB (PDAB) for the power management and current quality improvement, serving as a PCPD; and ③ an SMES serving as an energy storage system to carry out the energy exchange with the two DABs, for storing the surplus energy from the DC-DFIG under high wind speed and low load demand, and releasing energy under low wind speed and high load demand.

Fig. 1 System configuration of DC-DFIG-based WECS with integration of DAB-based DC-UPQC.

The unbalanced oscillation of DC voltage should also be considered. In AC systems, the dual control can be adopted in dealing with the unbalanced AC voltage. The core concept of this control system is to decompose the voltage/current signals into positive- and negative-sequence components and control these two signals separately [

53], [54]. However, this control system calls for additional phase-locked loop (PLL) and three-phase (abc) to dq rotation coordinate transformation (abc/dq transformation). If the dual control is introduced into the control strategy of DC converter, the control system will be significantly complicated. The proportional-integral plus resonant (PI-R) controller is also an alternative method for precisely tracking the AC current references [55]. Nevertheless, there are some defects in the PI-R controller. Firstly, the parameter estimation of the R regulator will become more complex since the R regulator is in parallel with the PI controller. Once the R controller is not precisely designed, the compensation accuracy will be influenced. Secondly, the utilization of PI-R controller will result in longer recovery time [56]. In this paper, to simplify the control strategy and effectively suppress the DC voltage oscillation generated by asymmetrical fault, a band-pass filter based DC dual control utilized in the SDAB and PDAB is proposed. The complicated PLL and abc/dq transformation are not required in the proposed DC dual control, but the voltage and current oscillations can be well-suppressed.

In summary, the contributions of this paper are listed as follows.

1) A DC-UPQC is proposed to simultaneously enhance the DC voltage and current qualities. Based on the modified structure and the support of ESDs, the proposed DC-UPQC has a wide range of four-quadrant V-I compensation. Meanwhile, the DC dual control is proposed in this paper to suppress the second-order voltage and current ripples.

2) An SMES is adopted as an ESD to regulate the power exchange via the two DABs of DC-UPQC. The structure, inductance, critical current, and capacity of SMES are estimated in this paper for the systematical application.

3) A DC-DFIG-based case study is carried out. The LVRT mechanism is analyzed in this paper, and the effectiveness of the proposed DC-UPQC in improving the LVRT capability and smoothing the output power is verified via simulation analysis.

4) Experimental analysis is also conducted to validate the circuit principle of the SDAB and PDAB, and demonstrate the feasibility of the proposed DC dual control.

The remainder of this paper is organized as follows. Section II introduces the modeling of DC-DFIG-based WECS and its parameter responses under the DC voltage sag and 100 Hz DC voltage oscillation. Section III presents the structure and circuit principles of the proposed DC-UPQC. Section IV introduces the control strategies of the proposed DC-UPQC. Section V shows the simulation and experimental results of the protection performance of DC-DVR in the DC-DFIG system. Section VI concludes the key findings of this paper.

II. Modeling of DC-DFIG and System Analysis

A. Behaviors of DC-DFIG Under DC Voltage Oscillation

Assuming that the DC-DFIG works under the normal operation and the terminal voltage $v_{d}$ can be regarded as a constant, the AC-side stator voltage $v_{s}$ of the DC-DFIG can be rectified by the diode rectifier as a three-step AC square wave, as shown in Fig. 2. Neglecting the initial phase, the three-phase stator voltages $v_{s a}$ , $v_{s b}$ , and $v_{s c}$ can be expressed according to Fourier decomposition as [

57]:

\{\begin{array}{l} v_{s a} (t) = \frac{2 V_{d}}{π} \{s i n (ω_{s} t) + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} s i n [(6 n \pm 1) ω_{s} t]\} \\ \begin{array}{l} v_{s b} (t) = \frac{2 V_{d}}{π} \cdot \\ \{s i n (ω_{s} t - \frac{2}{3} π) + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} s i n [(6 n \pm 1) (ω_{s} t - \frac{2}{3} π)]\} \end{array} \\ \begin{array}{l} v_{s c} (t) = \frac{2 V_{d}}{π} \cdot \\ \{s i n (ω_{s} t + \frac{2}{3} π) + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} s i n [(6 n \pm 1) (ω_{s} t + \frac{2}{3} π)]\} \end{array} \end{array}

(1)

Fig. 2 Waveform of single-phase stator voltage of DC-DFIG.

where $V_{d}$ is the amplitude of DC bus voltage; and $ω_{s}$ is the stator angular frequency.

Similar to the AC-DFIG system, the fundamental stator/rotor voltage and flux linkage equations of the DC-DFIG-based WECS can be established in the stationary $α β$ frame [

25], [58] as:

\{\begin{array}{l} v_{s α β} = R_{s} i_{s α β} + \frac{d ψ_{s α β}}{d t} \\ v_{r α β} = R_{r} i_{r α β} + \frac{d ψ_{r α β}}{d t} - j ω_{r} ψ_{r α β} \end{array}

(2)

\{\begin{array}{l} ψ_{s α β} = L_{s} i_{s α β} + L_{m} i_{r α β} \\ ψ_{r α β} = L_{m} i_{s α β} + L_{r} i_{r α β} \end{array}

(3)

where $R$ and $L$ are the resistance and inductance, respectively; $v$ , $i$ , $ψ$ , and $ω$ are the voltage, current, flux linkage, and angular frequency, respectively, of which the space vector forms are bold; subscripts $s$ and $r$ are the stator and rotor of DC-DFIG, respectively; subscripts $α$ and $β$ represent $α -$ and $β$ -axis values, respectively; and $L_{m}$ is the mutual inductance.

Combining (2) and (3), the space vector of dynamic rotor voltage can be expressed as:

v_{r α β} = (R_{r} - j ω_{r} σ L_{r}) i_{r α β} + σ L_{r} \frac{d i_{r α β}}{d t} + \underset{e_{r α β}}{\underset{︸}{\frac{L_{m}}{L_{s}} (v_{s α β} - R_{s} i_{s α β} - j ω_{r} ψ_{s α β})}}

(4)

where $e_{r α β}$ is the transient electromotive force (EMF) introduced by stator flux linkage; and $σ$ is the leakage coefficient, which can be expressed as:

σ = 1 - \frac{L_{m}^{2}}{L_{s} L_{r}}

(5)

According to (1), the space vector of stator voltage $v_{s α β}$ can be expressed as:

v_{s α β} = \frac{2 V_{d}}{π} [e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} e^{\pm j (6 n \pm 1) ω_{s} t}]

(6)

Neglecting the stator resistance, the space vector of flux linkage $ψ_{s α β}$ can be expressed as:

ψ_{s α β} = \int v_{s α β} d t = \frac{2 V_{d}}{π} [\frac{1}{j ω_{s}} e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{\pm 1}{j {(6 n \pm 1)}^{2} ω_{s}} e^{\pm j (6 n \pm 1) ω_{s} t}]

(7)

The space vector of rotor voltage can be then calculated after the manipulation of (4) and (7) as:

\begin{array}{l} v_{r α β} = (R_{r} - j ω_{r} σ L_{r}) i_{r α β} + σ L_{r} \frac{d i_{r α β}}{d t} - \frac{L_{m}}{L_{s}} R_{s} i_{s α β} + \\ \frac{2 L_{m} V_{d}}{L_{s} π} [s e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{(s - 1)}{6 n \pm 1} (1 \pm \frac{1}{6 n \pm 1}) e^{\pm j (6 n \pm 1) ω_{s} t}] \end{array}

(8)

where $s = (ω_{s} - ω_{r}) / ω_{s}$ is the slip of DC-DFIG.

Considering that an asymmetrical fault occurs in the AC grid, the connected DC voltage will experience a 100 Hz DC voltage oscillation along with the voltage sag [

59]. Assuming that a DC voltage oscillation occurs at

t = 0

and by ignoring the high-frequency harmonics, the space vectors of dynamic equation of stator voltage under the pre-fault condition

(t < 0)

and after the fault occurrence

(t \geq 0)

can be expressed as [4]:

v_{s α β} = \frac{2 V_{d}}{π} [e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} e^{\pm j (6 n \pm 1) ω_{s} t}] t < 0

(9)

v_{s α β} = \underset{v_{s α β +}}{\underset{︸}{\frac{2 V_{d 1}}{π} [e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} e^{\pm j (6 n \pm 1) ω_{s} t}]}} + \underset{v_{s α β -}}{\underset{︸}{\frac{2 V_{d 2}}{π} [e^{- j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{1}{6 n \pm 1} e^{\mp j (6 n \pm 1) ω_{s} t}]}} t \geq 0

(10)

where $V_{d 1}$ is the amplitude of the DC voltage; and $V_{d 2}$ is the amplitude of the AC components after a voltage dip. Equation (10) elaborates that the behavior of DC-DFIG under AC-side asymmetrical fault is similar to that of AC-DFIG. The positive- and negative-sequence stator voltages $v_{s α β +}$ and $v_{s α β -}$ will induce positive- and negative-sequence stator flux linkages, respectively. Meanwhile, a decayed DC component of the stator flux linkage will also be introduced under the DC voltage oscillation conditions [

54], [55].

According to (7) and (9), the steady-state space vectors of stator flux under the pre-fault condition $(t < 0)$ and after the fault occurrence $(t \geq 0)$ can be expressed as:

ψ_{s α β} = \frac{2 V_{d}}{π} [\frac{1}{j ω_{s}} e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{\pm e^{\pm j (6 n \pm 1) ω_{s} t}}{j {(6 n \pm 1)}^{2} ω_{s}}] t < 0

(11)

ψ_{s α β} = \frac{2 V_{d 1}}{π} [\frac{1}{j ω_{s}} e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{\pm e^{\pm j (6 n \pm 1) ω_{s} t}}{j {(6 n \pm 1)}^{2} ω_{s}}] + \frac{2 V_{d 2}}{π} [\frac{- 1}{j ω_{s}} e^{- j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{\mp e^{\mp j (6 n \pm 1) ω_{s} t}}{j {(6 n \pm 1)}^{2} ω_{s}}] t \geq 0

(12)

Note that the stator flux linkage cannot be abruptly changed when a fault occurs. Assuming that the RSC provides no excitation voltage for the DC-DFIG and is open-circuit, the dynamic changes of the stator flux linkage after the fault occurrence can be derived as:

\frac{d ψ_{s α β}}{d t} = v_{s α β} - \frac{R_{s}}{L_{s}} ψ_{s α β}

(13)

Combining (9)-(13), the transient stator flux can be expressed as:

ψ_{s α β} = \frac{2 V_{d 1}}{π} [\frac{1}{j ω_{s}} e^{j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{\pm e^{\pm j (6 n \pm 1) ω_{s} t}}{j {(6 n \pm 1)}^{2} ω_{s}}] + \frac{2 V_{d 2}}{π} [\frac{- 1}{j ω_{s}} e^{- j ω_{s} t} + \sum_{n = 1}^{\infty} \frac{\mp e^{\mp j (6 n \pm 1) ω_{s} t}}{j {(6 n \pm 1)}^{2} ω_{s}}] + \frac{2 (V_{d} - V_{d 1})}{π} [\frac{1}{j ω_{s}} e^{j ω_{s} t_{0}} + \sum_{n = 1}^{\infty} \frac{\pm e^{\pm j (6 n \pm 1) ω_{s} t_{0}}}{j {(6 n \pm 1)}^{2} ω_{s}}] e^{- t / τ_{s}} + \frac{2 (0 - V_{d 2})}{π} [\frac{- 1}{j ω_{s}} e^{- j ω_{s} t_{0}} + \sum_{n = 1}^{\infty} \frac{\mp e^{\mp j (6 n \pm 1) ω_{s} t_{0}}}{j {(6 n \pm 1)}^{2} ω_{s}}] e^{- t / τ_{s}} t \geq 0

(14)

where $τ_{s} = L_{s} / R_{s}$ is the time constant of stator; and $t_{0}$ is the fault occurrence time. In (14), we set $t_{0} = 0$ .

By substituting (14) into (8), transferring the space vector of rotor voltage into rotor reference frame, and ignoring the influence of the stator current, the EMF in (4) under the DC bus voltage sag with oscillation can be re-written as:

e_{r α β}^{r} = \frac{L_{m}}{L_{s}} \{\frac{2 V_{d 1}}{π} [s e^{j ω_{s l i p} t} + \sum_{n = 1}^{\infty} \frac{s - 1}{6 n \pm 1} (1 \pm \frac{1}{6 n \pm 1}) e^{\pm j (6 n \pm 1) ω_{s l i p} t}] + \frac{2 V_{d 2}}{π} [(2 - s) e^{- j (2 - s) ω_{s} t} + \sum_{n = 1}^{\infty} \frac{(1 - s) e^{\mp j (6 n \pm 1) ω_{s l i p} t}}{6 n \pm 1} (1 \pm \frac{1}{6 n \pm 1})] - \frac{2 (V_{d} - V_{d 1})}{π} [(1 - s) e^{j ω_{s} t_{0}} + \sum_{n = 1}^{\infty} \frac{\pm (1 - s)}{{(6 n \pm 1)}^{2}} e^{\pm j (6 n \pm 1) ω_{s} t_{0}}] e^{- t / τ_{s}} e^{- ω_{r} t} - \frac{2 (0 - V_{d 2})}{π} [(s - 1) e^{- j ω_{s} t_{0}} + \sum_{n = 1}^{\infty} \frac{\mp (s - 1)}{{(6 n \pm 1)}^{2}} e^{\mp j (6 n \pm 1) ω_{s} t_{0}}] e^{- t / τ_{s}} e^{- ω_{r} t}\}

(15)

where $ω_{s l i p} = ω_{s} - ω_{r}$ . Equation (15) shows that the dynamic process of rotor voltage is significantly complex. Neglecting the high-frequency component, three compositions can be observed in the transient rotor EMF $e_{r α β}^{r}$ : ① an AC component that rotates anticlockwise at a speed of $ω_{s l i p}$ ; ② an AC component that rotates clockwise at a speed of $(2 - s) ω_{s}$ ; and ③ an AC component that rotates clockwise at a speed of $ω_{r}$ , and decays with the time constant $τ_{s}$ . The second and third components are transient signals that will also lead to a massive oscillation of the EM torque and damage of the gearbox and converter.

B. Behaviors of DC-DFIG Output Power under DC Voltage Oscillation

Under the DC voltage oscillation, the amplitude of DC voltage will be changed from $V_{d}$ to $V_{d 1} + V_{d 2} s i n (2 ω_{s} t)$ , by only considering the $2 ω_{s}$ frequency oscillation. Accordingly, the output current of DC-DFIG can be expressed as $I_{d 1} + I_{d 2} s i n (2 ω_{s} t + φ_{0})$ with consideration of the nonlinear elements in the DC transmission cable, where $φ_{0}$ is the shifting phase between the DC voltage and current oscillations. The output power of DC-DFIG-based WECS can be then derived as:

P_{d} = (V_{d 1} + V_{d 2} s i n (2 ω_{s} t)) (I_{d 1} + I_{d 2} s i n (2 ω_{s} t + φ_{0})) = P_{d 1} + P_{d s i n 2} s i n (2 ω_{s} t) + P_{d s i n 4} s i n (4 ω_{s} t)

(16)

where subscripts 1, sin2, and sin4 of $P_{d}$ represent the DC, $2 ω_{s}$ , and $4 ω_{s}$ components of the output power, respectively. Since the amplitudes of DC voltage and current oscillations ( $V_{d 2}$ and $I_{d 2}$ ) are generally small, the $4 ω_{s}$ component can be neglected in the analysis. Equation (16) reveals that there will be no oscillation of voltage, current, and power in the transmission line under the normal conditions. With unbalanced disturbances, conversely, these coefficients are not equal to zero, and the main power oscillation is with a frequency of $2 ω_{s}$ .

Synthesizing the above analysis, a hardware device is required for power compensation due to the intermittent and volatility of wind energy. The regulation of DC terminal voltage is also necessary to improve the LVRT capability of the DC-DFIG. Meanwhile, an advanced control strategy is also required to suppress the voltage, current, and power oscillations.

III. Circuit Principle of DAB-based DC-UPQC

A. System Configuration

The detailed model of DC-UPQC is shown in Fig. 3, where $v_{d}$ , $v_{g}$ , and $v_{c}$ are the DC-DFIG-side, grid-side, and SDAB-side volages, respectively; $i_{d}$ , $i_{g}$ , and $i_{c}$ are the DC-DFIG-side, grid-side, and PDAB-side currents, respectively; $v_{d c}$ is the bus voltage of ESD; $i_{S C}$ is the SMES current; $v_{H 1}$ - $v_{H 4}$ and $i_{H 1}$ - $i_{H 4}$ are the voltages and currents of the bridges 1-4 at the high-frequency side, respectively; $v_{2}$ and $i_{4}$ are the output voltage and current of bridges 2 and 4, respectively; and $v_{l f 2}$ is the inductance voltage of L_f₂. The system consists of two main parts: SDAB and PDAB. The output port of PDAB is serial with the DC transmission line near the DC microgrid, while the output port of SDAB is in parallel with the DC transmission line in front of the terminal of the DC-DFIG-based WECS. The input ports of the two DABs are connected, formulating an ESD bus, where the SMES and its converter are connected.

Fig. 3 Detailed configuration of proposed SMES-based DC-UPQC.

The SDAB is to maintain the voltage profile under grid faults. According to Fig. 1, the relationship of the DC-DFIG-side voltage $v_{d}$ , grid-side voltage $v_{g}$ , and compensation voltage $v_{c}$ is:

v_{d} = v_{g} + v_{c}

(17)

Equation (17) reveals that the SDAB can introduce a certain DC voltage in series with the DC cable under DC voltage quality events. It can improve the LVRT capability of the DC-DFIG and protect crucial elements of the system.

The PDAB has two functions: ① compensating the variable output power of DC-DFIG under wind gust situations; and ② enhancing the current and output power qualities of DC-DFIG under DC fault events. As shown in Fig. 1, the relationships of the current and power at the DC-DFIG side, PDAB side, and grid side can be expressed as:

i_{d} + i_{c} = i_{g}

(18)

P_{d} + P_{c} = P_{g}

(19)

B. SDAB

To simplify the analysis of the circuit principle, the SDAB and PDAB are considered as single phase-shifting (SPS) control strategies. Figure 4 shows the crucial parameter responses of the SDAB, where $T_{h s}$ represents the half period; and $φ_{s}$ is the ratio of shifting phase in SDAB. Under the control by the SMES and DC/DC converter, the DC bus voltage of DC-UPQC $V_{d c}$ can be considered as a constant. The relationship among of $φ_{s}$ , $v_{c}$ , and $V_{d c}$ can be expressed as:

v_{c} = - 2 [φ_{s} n_{s} V_{d c} + (\frac{1}{2} - φ_{s}) (- n_{s} V_{d c})] = (4 φ_{s} - 1) n_{s} V_{d c}

(20)

Fig. 4 Operation of SDAB for voltage sag compensation and voltage swell suppression. (a) Voltage sag compensation. (b) Voltage swell suppression.

where $n_{s}$ is the turn ratio of the high-frequency transformer in the SDAB. Equation (20) claims that $φ_{s}$ is correlated linearly with the output voltage of SDAB $v_{c}$ . When $φ_{s}$ is equal to 0.5, the output voltage of SDAB is equal to zero. When $φ_{s}$ is in a range of [0, 0.5), a backward voltage compensation can be provided by the SDAB in a range of $[- n V_{2}, 0)$ for voltage sag compensation, as shown in Fig. 4(a). When $φ_{s}$ is in the range of (0.5, 1], a forward voltage compensation will be generated by the SDAB, and the compensation is in a range of $(0, n V_{2}]$ for voltage swell suppression, as shown in Fig. 4(b).

There is an external inductance $L_{f 2}$ that can be used to limit the rate of current increment and confine the current stress of SDAB. The current stress is equal to the peak value of $i_{H 2}$ , defined as $I_{p}$ , which can be also observed in Fig. 4. Assuming that $i_{l o a d}$ is zero, the value of $I_{p}$ can be calculated as:

\{\begin{array}{l} L_{f 2} \frac{- I_{p} - I_{p}}{φ_{s} T_{s}} = v_{l f 2} - 2 n_{2} V_{d c} \\ L_{f 2} \frac{I_{p} - (- I_{p})}{(0.5 - φ_{s}) T_{s}} = v_{l f 2} \end{array}

(21)

I_{p} = φ_{s} (1 - 2 φ_{s}) \frac{n_{2} V_{d c}}{L_{f 2} f_{s}}

(22)

where $T_{s} = 1 / f_{s}$ is the switching period, and $f_{s}$ is the switching frequency; and $v_{l f 2}$ is the voltage across the inductance $L_{f 2}$ . According to (22), the inductance $L_{f 2}$ can be used to control the current stress of the SDAB.

The relationships among the output voltage of SDAB $v_{c}$ , inductance voltage $v_{l f 2}$ , and output voltage of bridge 2 $v_{2}$ can be expressed as:

v_{c} = v_{2} - v_{l f 2}

(23)

C. PDAB

The working principle of PDAB is consistent with the traditional DAB investigated in [

60]-[62]. There is a series inductor

L_{f 4}

that controls the current rise and decides the power level of PDAB. The operation of PDAB under the backward and forward current flow conditions is shown in Fig. 5. The compensation current

i_{c}

can be obtained from

i_{4}

with the function of LC filter

C

₄ and

L_{o u t}

Fig. 5 Operation of PDAB under backward and forward current flow conditions. (a) Under backward current flow condition. (b) Under forward current flow condition.

The inductance current $i_{H 4} (t)$ can also be expressed as:

\frac{d i_{H 4} (t)}{d t} = \frac{v_{H 4} (t) - v_{H 3} (t)}{L_{f 4}}

(24)

Considering that the average current flowing through the inductance $L_{l 2}$ in a period is considered as zero; the power delivery of PDAB in a period of $T_{s}$ can be derived by:

P_{H 4} = \frac{1}{T_{s}} \int_{0}^{T_{s}} v_{H 4} i_{H 4} (t) d t = \frac{n_{p} v_{d} V_{d c}}{f_{s} L_{f 4}} φ_{p} (1 - 2 φ_{p})

(25)

where $n_{p}$ is the turn ratio of the PDAB; and $φ_{p} \in [- 0.5, 0.5]$ is the ratio of shifting phase in PDAB. During the normal operation, the magnitudes of $V_{d c}$ and $v_{d}$ can be considered as constants. The filter inductance $L_{f 4}$ controls the current rise and can be used to estimate the capacity of PDAB.

D. Design of SMES

As one of few current sources, SMES is an emerging technology that can store the magnetic energy in a superconducting coil (SC), and release the stored energy when required. Compared with other commercial ESDs such as battery energy storage (BES) with a low-power capacity, the high-power capacity of SMES makes it more suitable for MW-class applications.

Moreover, the cost of power loss in the battery is considerable. As for the supercapacitor, it is necessary to keep the energy uniformity of each cell, so the additional cost of the online condition monitoring and the voltage/current balancing control should also be considered. In comparison, the SMES is actually an individual SC. Therefore, the voltage balancing control and condition monitoring are not necessary. Moreover, if one supercapacitor component breaks, the performance and stabilization of supercapacitor will be influenced. Conversely, the SMES has better stability as an ESD due to its individual structure [

63], [64].

The expensive capital cost of SMES is always criticized. Recently, many new structures of SMES have been designed to increase the critical current, reduce the usage of superconducting tape, and lower the cost. Among the existing investigations, the step-shaped solenoidal coil obviously enlarges the critical current (1.4 times that of the rectangular-shape coil) and decreases the amount of tape usage (80% of the rectangular-shape coil) [

65], [66]. However, the above structures are based on 1G superconducting strip. As the newest research achievement, the 2G-strip-based varying-axial-gap structure proposed in [67] and adopted in this paper is proven to enlarge around 40% energy capacity for an MJ-class SMES case compared with the regular-shape coil.

Figure 6(a) shows a structure of a designed varying-axial-gap solenoidal SC among certain pancakes. The designed SC is made up of $Q$ single pancakes. Among them, $2 m$ single pancakes have a fundamental gap of $g$ and a gap increment of $Δ x$ ; while $Q - 2 m$ single pancakes have a constant axial gap of $d$ . The wire of each single pancake is winded using $N$ turns, and the inner radius and outer radius of each pancake are $R_{i}$ and $R_{o}$ , respectively.

Fig. 6 Design of SMES. (a) Structure of designed varying-axial-gap solenoidal SC. (b) Electrical connections of eight SMES elements.

After the optimal design and calculation, the structural parameters of the designed varying-axial-gap solenoidal SC are $Q = 80$ , $N = 19$ , $R_{i} = 0.5$ m, $R_{o} = 0.507$ 6 m, $m = 11$ , $Δ x = 1$ mm, $g = 1$ mm, and $d = 0$ , respectively. However, due to the internal packaging issue of the strip in practice, the constant axial gap can be considered as $d \approx 0.8$ mm. The usage of the superconducting tape is about 5 km. With these parameters, the critical current of the designed SMES element is about 900 A, and the inductance and capacity of the designed SMES element are 2.57 H and 1.04 MJ, respectively.

In this paper, the adopted SMES device contains eight designed SMES elements. The electrical connections of the designed SMES are shown in Fig. 6(b). The eight SMES elements are firstly divided into two components, and each component consists of four SMES elements connected in series. The critical inductance and current of each component are 10.28 H/900 A, respectively. The two components are further connected in parallel to compose a 5.14 H/1800 A SMES unit, whose capacity is 8.32 MJ. The designed composite SMES element can meet the capacity requirement considering the demanded wind power compensation capacity.

IV. Control Strategies

It is necessary to introduce an oscillation regulator to mitigate the DC voltage, current, and power oscillations under unbalanced AC-side grid faults. Figures 7 and 8 show the control strategies of the proposed SMES-based DC-UPQC.

Fig. 7 Filters used in proposed SMES-based DC-UPQC. (a) Bode diagram of band-trap filter. (b) Bode diagram of band-pass filter.

Fig. 8 Control diagram of proposed SMES-based DC-UPQC.

A. Control of SDAB

To separately regulate these two voltage components, as depicted in Figs. 7 and 8, the terminal voltage of sampled DC-DFIG $v_{d}$ can be decomposed to a DC component $v_{d 1}$ by the band-trap filter, and an oscillatory component $v_{d 2}$ by the band-pass filter. The two filters are used to implement the error-free tracking control. The open-loop transfer function of the band-trap filter can be expressed as:

G (s) = \frac{s^{2} + {(2 π f)}^{2}}{s^{2} + ω_{0} s + {(2 π f)}^{2}}

(26)

where $f = 100$ Hz; and $ω_{0}$ is the cut-off frequency, which can be adjusted to decrease the sensitivity of the frequency fluctuation. Figure 7(a) shows the bode diagram of the band-trap filter when $ω_{0}$ is equal to $2 \sqrt[]{2} π f$ rad/s. The difference between the actual and reference signals ( $v_{d 1}$ and $v_{d 1}^{*}$ ) is considered as the input signal of PI controller, while the reference signal $v_{d 1}^{*}$ is assumed to be equal to the rated terminal voltage of DC-DFIG.

To precisely obtain the oscillatory signal, a band-pass filter is introduced, and the open-loop transfer function of the band-pass filter is expressed as:

G (s) = \frac{2 π f s}{s^{2} + ω_{0} s + {(2 π f)}^{2}}

(27)

The bode diagram of the open-loop band-pass filter is shown in Fig. 7(b) with the cut-off frequency of $ω_{0} = 10$ rad/s. The oscillation signal $v_{d 2}$ is then carried out from a virtual $α β / d q$ transformation, which is adopted via a $π / 2$ transport delay model. The process can be expressed mathematically as:

v_{d 2 d q} = v_{d 2 α β} e^{- j ω t}

(28)

The obtained signals $v_{d 2 d}$ and $v_{d 2 q}$ are DC signals, which are easy to be regulated by PI controllers. Since the generated dq signals $v_{d 2 d}$ and $v_{d 2 q}$ are separately regulated, the input angle frequency of the dq transform does not call for the initial angle phase and PLL to track the oscillatory voltage. The reference dq signals of the oscillation components $v_{d 2 d}^{*}$ and $v_{d 2 q}^{*}$ are equal to zero.

After the PI regulation, a $d q / α β$ inverse transformation is utilized, and the obtained $α$ -axis component is used as the output signal of the oscillation regulator. The phase-shifting control can be implemented by adding the output signals of the DC regulator and the oscillation regulator. Note that the $α$ -axis component is an AC signal with a rotating frequency of 100 Hz. When a voltage oscillation occurs, the ratio of the shifting phase contains two components, i.e., a DC component for voltage magnitude compensation and an AC component for voltage oscillation suppression.

B. Control of PDAB

The PDAB also uses the similar control structure as SDAB. There are two alternative control targets designed for power compensation and current quality enhancement, respectively: ① target 1: constant power control; and ② target 2: constant current control.

Under the constant power control, the grid-side power $P_{g}$ is considered as the input signal; while under the constant current control, the output current of DC-DFIG $i_{d}$ is assumed as the input signal. Similar to the control of SDAB, the reference signals of the DC power and current ( $P_{g 1}^{*}$ and $i_{d 1}^{*}$ ) are equal to the rated power and current of the DC-DFIG, respectilvely, and the reference signals of the oscillation components ( $P_{g 2 d}^{*}$ and $P_{g 2 q}^{*}$ or $i_{d 2 d}^{*}$ and $i_{d 2 q}^{*}$ ) are equal to zero.

C. Control of SMES

The function of SMES is to sustain the DC bus voltage as a DC power supply of DC-UPQC. The control of the DC-DC converter is shown in Fig. 8. The DC bus voltage $v_{d c}$ is sampled, and the difference of the actual and reference signals ( $v_{d c}$ and $v_{d c}^{*}$ ) is fed into the PI controller. Finally, a duty cycle can be generated in the range of [0, 1] by adding the output signal of the PI controller to an offset constant of 0.5.

V. Simulation Results

A 1.5 MW DC-DFIG-based WECS with the integration of the proposed SMES-based DC-UPQC using MATLAB/Simulink is shown in Fig. 1. In the study model, the DC-DFIG is connected to a 1 kV DC source. Initially, the DC-DFIG works at a steady state, and the output power is the rated power (1.0 p.u.). The slip of the DC-DFIG is set to be -0.2. The inductance, critical current, and capacity of the SMES are 5.14 H, 1800 A, and 8.32 MJ, respectively, and the initial current of SMES is 1272 A. The turn ratios of the SDAB and PDAB $n_{p}$ and $n_{s}$ in the DC-UPQC are both 2:1, which means the DC bus voltage of DC-UPQC is 500 V. The filter inductances of bridegs 2 and 4 $L_{l 2}$ and $L_{l 4}$ are 200 $μ H$ and 10 $μ H$ , respectively. The current compensation range is about [-1250 A, 1250 A] with the adopted filter inductances. It means that the unsteady output power resulting from the volatility of wind energy can be smoothed by the PDAB when the output power of DC-DFIG fluctuates in the range of [0.25 MW, 2.75 MW].

To give a round performance validation of the proposed targets, three cases are analyzed in the simulation and listed as follows: ① Case 1: without any control system; ② Case 2: with the proposed DC-UPQC but without the DC dual control; and ③ Case 3: with the proposed DC-UPQC and DC dual control.

A. Behaviors of DC-DFIG with Variable Wind Speeds

Under variable wind speeds, the PDAB plays a leading role in smoothing the output power of DC-DFIG.The two control targets are both available for output power mitigation since the DC source voltage can be regarded as a constant during the normal operation. Figure 9 shows the wind speed variation, power conditions of the DC-DFIG, DC-UPQC, and DC source, and the response of the SMES current with variable wind speeds. The 60 s emulated wind speed data varying from 11 m/s to 19 m/s based on the Kaimal wind speed model [

68] are adopted in the simulation. Besides, some assumptions are made with variable wind speeds: ① there is no power quality disturbance with variable wind speeds; ② an average wind speed of 14 m/s is considered as the nominal speed of DC-DFIG; and ③ there is no extremely high-speed wind gust or breezeless condition.

Fig. 9 Wind speed variation, power of DC-DFIG, DC-UPQC, and DC source, and SMES current with variable wind speeds. (a) Wind speed. (b) Responses of output power of DC-DFIG, grid-side output power, and injected power of PDAB. (c) SMES current during power compensation process.

As illustrated in Fig. 9(b), the output power of DC-DFIG will fluctuate in the range of [0.8 p.u., 1.4 p.u.] following the wind speed variations. With the proposed compensation strategy, the PDAB of DC-UPQC will inject a specific current to keep the total output power of DC-DFIG and DC-UPQC at a constant level (1.0 p.u.), smoothing the unsteady output power and eliminating the potential system stability issues. Reflected by the SMES current, the state of charge (SOC) of SMES will fluctuate between 10% and 90% to adjust the total output power with variable wind speeds. Figure 9(c) reveals that the designed SMES has a sufficient capacity and a compelling performance in dealing with the power fluctuation with time-varying wind speeds.

B. Behaviors of DC-DFIG Under AC-side Line-to-line Fault

Figure 10 shows the parameter responses of the DC-DFIG under DC voltage sag with oscillation. At $t = 0.5$ s, 80% voltage depth is assumed to take place due to line-to-line fault in phases A and B. Without any controller, the terminal voltage of DC-DFIG falls from 1 kV to 466.7 V. Meanwhile, a 100 Hz voltage oscillation appears with the amplitude of 176.3 V.

Fig. 10 Responses of terminal voltage, EM torque, magnitudes of stator and rotor currents, output current and power of DC-DFIG under DC voltage sag with oscillation. (a) Without any controller in Case 1. (b) Under constant power control in Cases 2 and 3. (c) Under constant current control in Cases 2 and 3.

As shown in Fig. 10(a), the crucial parameters, including EM torque, stator current, and rotor current, are all beyond the maximum permitted values (2.0 p.u.) along with significant oscillations. Such oscillations will lead to a severe heating problem in the machine and may damage the expensive gearbox of the wind turbine. As a result, there is a substantial spike in the output DC current and power at the beginning of the fault occurrence. Meanwhile, there is also a huge 100 Hz oscillation in the output DC current and power.

As shown in Fig. 10(b) and (c), the application of the DC-UPQC considerably improves the LVRT capability of DC-DFIG and the qualities of DC current and power. However, without the DC dual control, the oscillations of the DC voltage, current, and power cannot be eliminated (red curves in Fig. 10(b) and (c)). The total harmonic distortion (THD) spectrum of the DC voltage, output current, and power is shown in Fig. 11. Under the constant power control in Case 2, there is still a 100 Hz oscillation in the DC output power, and its THD is about 7.75% of the DC component. Under the constant current control in Case 2, the DC output current contains a 100 Hz current oscillation, whose THD is about 4.05% of the current DC component. Without the DC dual control, the THD of the DC-DFIG terminal voltage is 1.83%, which still has a potential possibility of system component destruction.

Fig. 11 THD spectrum in Cases 1-3. (a) DC voltage of DC-DFIG. (b) Output current under constant current control. (c) Output power under constant power control.

With the DC dual control, the DC power and current quality can be further enhanced under the constant power and current control, respectively (green curves in Fig. 10(b) and (c)). It can be observed from the THD spectrum that the 100 Hz oscillations of the DC current and power are almost cleared. The THD of the DC power is 1.33% under the constant power control, while the THD of the DC current is 0.44% under the constant current control. With the DC dual control in SDAB, the THD of the DC-DFIG terminal voltage is only about 0.06%, which reduces the tripping risk of the DC-DFIG and protects the crucial elements within the system.

Figure 12 shows the responses of SMES current with the two control targets in Cases 2 and 3. Under the constant power control, the absorbed energy will be simultaneously released by PDAB to keep the output DC power at its rating level. Therefore, the SMES current is almost unchanged, varying from 1271.8 A to 1274 A during the whole transient process, as shown in Fig. 12(a). Under the constant current control, the output DC current to the DC source is controlled as the rated current, and no compensation power is injected from the PDAB. The SMES only absorbs the surplus energy from the SDAB, and the SMES current raises from 1272 A (at $t = 0.5$ s) to 1331 A (at $t = 1$ s). Meanwhile, the SMES current slightly fluctuates due to the power fluctuation caused by the DC voltage oscillation, as shown in Fig. 12(b).

Fig. 12 Response of SMES current in Cases 2 and 3. (a) Under constant power control. (b) Under constant current control.

C. Experimental Results

A 50 V/5 A experimental setup is established to prove the effectiveness of the proposed DC dual control. The platform is shown in Fig. 13. To simplify the experimental setup, a DC source is served as the DC power supply of the DC-UPQC. Circuit principles of these two structures are also verified in this experiment. To avoid unnecessary risks in the experiment, the voltage sag and swell are generated via a voltage divider instead of the short-circuit fault. In this experiment, the turn ratio of the high-frequency transformer is $2 : 1$ ; the DC power supply of the DC-UPQC is set to 25 V; the filter inductances $L_{f 2}$ and $L_{f 4}$ are 200 $μ H$ and 100 $μ H$ , respectively, which means the maximum power output capacity of the PDAB is in the range of [-625 W, 625 W].

Fig. 13 Experimental setup. (a) Schematical diagram of UPQC. (b) Experimental platform of DC-UPQC.

1)　Circuit Principle

Figure 14 shows the experimental results of the SDAB under the normal operation and PDAB under 5 A current compensation. As can be observed, the waveforms of the SDAB and PDAB are consistent with the theoretical waveforms shown in Figs. 4 and 5, respectively. Therefore, the experiment proves the correctness of the basic principles of the SDAB and PDAB introduced in Section III.

Fig. 14 Experimental results of circuit principle. (a) Circuit principle of SDAB under normal operation. (b) Circuit principle of PDAB under 5 A compensation.

2)　Voltage and Current Compensation

Figure 15 shows the parameters of load voltage $v_{l o a d}$ , compensation voltage $v_{c}$ , grid-side current $i_{g}$ , and compensation current $i_{c}$ under voltage sag/swell compensation and load variation condition with the protection of DC-UPQC. The control targets of the PDAB and SDAB in DC-UPQC are constant source current and constant load voltage, respectively.

Fig. 15 Experimental results of voltage disturbances and load variations. (a) 25% voltage sag. (b) 25% voltage swell. (c) 250 W load connection compensation. (d) 125 W load removal compensation.

As shown in Fig. 15(a) and (b), under disturbances of 25% voltage sag and 25% voltage swell, respectively, the load voltage $v_{l o a d}$ can be well-maintained via SDAB to the nominal value. In Fig. 15(c) and (d), a ±2.5 A load variation is introduced, lasting for 200 ms. At that time, the PDAB will introduce a compensation current into the DC bus, and the grid-side current can be maintained at 5 A.

3)　Oscillation Suppression

Figure 16 shows the responses of SDAB parameters (grid-side voltage $v_{g}$ , compensating voltage $v_{c}$ , load voltage $v_{l o a d}$ , and load current $i_{l o a d}$ ) under the DC voltage sag with oscillation.

Fig. 16 Experimental results for SDAB under DC voltage sag with oscillation (under either constant power or current control). (a) Case 2. (b) Case 3.

In Fig. 16(a), the DC dual control is not used. As can be observed, although the amplitude can be accurately enhanced to the rated value, the oscillation cannot be well-suppressed. With the DC dual control, both the DC voltage amplitude and the voltage oscillation can be well-compensated within 100 ms, as shown in Fig. 16(b). Therefore, the proposed DC dual control has a better dynamic performance than the traditional control when dealing with the second-order voltage ripple.

Figure 17 shows the responses of PDAB parameters (grid-side current $i_{g}$ , compensation current $i_{c}$ , load current $i_{l o a d}$ , load voltage $v_{l o a d}$ , and load power $P_{l o a d}$ ) under DC voltage oscillation sag. Figure 17(a) and (b) shows the results of constant power control in Cases 2 and 3, respectively. Whereas, Fig. 17 (c) and (d) show the results of constant current control in Cases 2 and 3, respectively. It is evident that the load current and power oscillations cannot be precisely eliminated with traditional control methods. With the DC dual control, the oscillations of the load current and power can be cleared rapidly, and only a few high-order harmonics exist in the waveforms of load current and load power. The experiment results for PDAB prove the effectiveness of the two control targets and the DC dual control in PDAB.

Fig. 17 Experimental results for PDAB under DC voltage sag with oscillation. (a) Constant power control in Case 2. (b) Constant power control in Case 3. (c) Constant current control in Case 2. (d) Constant current control in Case 3.

D. Comparison with Other DC Control Strategies

Table I shows a comparison between the proposed DC-UPQC and other existing DC control strategies, including the control method in [

39], DC-PFC in [40], IUPS in [43], SVR in [45], and SMES-TLSVR in [46].

TABLE I Comparison Between Proposed DC-UPQC and Existing DC Control Strategies

Strategy	Voltage sag	Voltage swell	Power regulation	Voltage oscillation	Current oscillation
Method in [39]	$\times$	$\times$	$\times$	$\sqrt$	$\sqrt$
DC-PFC [40]	$\times$	$\times$	$\sqrt$	$\times$	$\times$
IUPS [43]	$\sqrt$	$\sqrt$	$\times$	$\times$	$\times$
SVR [45]	$\sqrt$	$\sqrt$	$\times$	$\times$	$\times$
SMES-TLSVR [46]	$\sqrt$	$\sqrt$	$\times$	$\times$	$\times$
Proposed DC-UPQC	$\sqrt$	$\sqrt$	$\sqrt$	$\sqrt$	$\sqrt$

Note: $“ \times ”$ and $“ \sqrt ”$ represent the device is without and with this function, respectively.

The attractive features of the proposed DC-UPQC can be summarized as follows.

1) Unlike other traditional DC controllers, the proposed DC-UPQC system has superior features in terms of performing the functions of voltage sag/swell mitigation, power supplement, and voltage and current harmonics elimination.

2) The proposed DC-UPQC system provides a new strategy for ESDs such as SMES to interface with the LV DC microgrid to simultaneously improve the voltage quality simultaneously, smooth the fluctuated power of renewable energy, and suppress voltage and current oscillations during AC voltage unbalance events.

VI. Conclusion

An SMES-based DC-UPQC is proposed in this paper. The topologies of its compositions, i.e., SDAB, PDAB, and SMES, are fully described. The DC dual control strategies of the DC-UPQC with consideration of DC and oscillation regulators are presented.

Parameter responses of the DC-DFIG and grid-side power oscillations under DC voltage sag with oscillation are analyzed. With the connection of the proposed controller, simulation results show that all crucial parameters of the DC-DFIG can be well constricted within their maximum permitted values. With the large-power SMES, the proposed DC dual control of the SDAB and PDAB can also be well-implemented under DC voltage oscillations.

An experiment is carried out to verify the proposed DC dual control of the DC-UPQC. Experimental results verify the correctness of the circuit principle of the SDAB and PDAB, and the effectiveness of the modified control strategies is also validated.

Conclusively, the proposed scheme has several outstanding features over other existing DC protection devices. This includes straightforward structure, capability of simultaneously handling the DC voltage and current quality with wide compensation range, and providing improved control strategy for voltage, current, and power oscillation suppression.

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