Analysis and Control of Modular Multi-terminal DC Power Flow Controller with Fault Current Limiting Function

Qianming Xu; Xinyu Huang; Xu Chu; Mingshen Li; Zhikang Shuai; Chunming Tu; Josep M. Guerrero

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Analysis and Control of Modular Multi-terminal DC Power Flow Controller with Fault Current Limiting Function PDF

- ORCID：
Qianming Xu
✉
- ORCID：
Xinyu Huang
✉
- ORCID：
Xu Chu
✉
- ORCID：
Mingshen Li
✉
- ORCID：
Zhikang Shuai
✉
- ORCID：
Chunming Tu
✉
- ORCID：
Josep M. Guerrero
✉

College of Electrical and Information Engineering, Hunan University, Changsha, China； Department of Energy Technology, Aalborg University, Aalborg, Denmark

Updated：2021-11-23

DOI：10.35833/MPCE.2020.000876

OUTLINE

Abstract

In order to overcome the problems of power flow control and fault current limiting in multi-terminal high voltage direct current (MTDC) grids, this paper proposes a modular multi-terminal DC power flow controller (MM-DCPFC) with fault current limiting function. The topology structure, operation principle, and equivalent circuit of MM-DCPFC are introduced, and such a structure has the advantages of modularity and scalability. The power balance mechanism is studied and a hierarchical power balance control strategy is proposed. The results show that MM-DCPFC can achieve internal power exchange, which avoids the use of external power supply. The fault characteristics of MM-DCPFC are analyzed, fault current limiting and self-protection methods are proposed, and the factors affecting the current limiting capability are studied. The simulation models are established in PLECS, and the simulation results verify the effectiveness of MM-DCPFC in power flow control, fault current limiting, and scalability. In addition, a prototype is developed to validate the function and control method of MM-DCPFC.

Keywords

Fault current limiting; multi-terminal high voltage direct current (MTDC) grid; power balance; DC power flow controller

I. Introduction

IT is beneficial for solving the problem of energy shortage by developing renewable energy vigorously [

1], [2]. Multi-terminal high voltage direct current (MTDC) grid, which is highly reliable and stable relative to conventional AC grid, is one of the most effective technologies to solve the issues of grid integration, transmission, and absorption of renewable energy [3], [4]. However, there are still problems in MTDC system such as power flow regulation and fault current limitation, which need to be further studied.

In complex MTDC grids such as the meshed DC grid, insufficient degrees of freedom of power flow control will lead to line overloading and increased load loss [

5]. The utilization of DC power flow controllers (DCPFCs) can address this problem and improve the power flow control capacity of MTDC grids [6], [7]. The principle of DCPFCs can be divided into two categories: changing the resistance or voltage of the line [8], [9], where the variable voltage type DCPFC can be divided into three categories: DC transformers, series adjustable voltage source, and interline DC power flow controller (IDCPFC). IDCPFC, as a new configuration, can be used to distribute power flow between two or more lines. Since the power exchange is completed internally without external power supply, IDCPFC has great advantages over the other two DCPFCs.

A dual H-bridge IDCPFC is proposed in [

10], which has the advantages of simple structure, low cost, and easy control, but it will introduce large ripples to the line current. The IDCPFC in [11] connects a capacitor in series on each of the two lines, and realizes power exchange through an inductor or a DC/DC converter, which improves the line current ripple problem. The topology in [11] is further improved in [12], which can be applied to the condition of current reversal. The output voltage levels of IDCPFCs proposed in [10]-[12] are limited because they are all single-module structures. The multi-module IDCPFC proposed in [13] and [14] is composed of three-phase converters and an AC transformer, which is large in size and high in cost. The cascaded form of dual H-bridge topology is proposed in [15], in which high-voltage switches are added to realize the isolation of the capacitor voltage. In [16], a ring type IDCPFC is proposed, which has better redundancy and flexibility.

Another major challenge hindering the development of MTDC grids is fault protection [

17]. As a series equipment, the damage of IDCPFC under fault conditions will lead to current flow interruption and even endanger the whole DC system [18], [19]. However, IDCPFCs in [10]-[16] only focus on the steady-state operation principle, and cannot deal with DC faults. Therefore, it is necessary to study the fault operation characteristic and protection mechanism of DCPFC. In addition, due to the rapid rise of fault current and the limited response time of DC circuit breakers (DCCBs), it is difficult to interrupt the fault current. Hence, fault current limitation is one of the key points of DC fault research. The basic principle of DCPFC is to change the line impedance or voltage, which is similar to the principle of current limiter. If this impedance or voltage characteristic can be used under fault conditions, DCPFC can limit the fault current, which is beneficial to reduce the interruption current of DCCBs, so as to reduce the cost.

This paper proposes a modular multi-terminal DC power flow controller (MM-DCPFC), which can realize the free regulation of the current between multiple lines and perform a current limiting function when a short-circuit fault occurs in the DC system. The main contributions are as follows. ① The modular structure offers strong scalability. MM-DCPFC can increase the power flow regulation range by expanding the number of sub-modules (SMs) and realize the power flow control between multiple lines by expanding the number of arms without installing multiple DCPFCs, which is more economical. ② Since MM-DCPFC achieves its power balance through a hierarchical control strategy, it does not need external power supply, nor does it need transformers, inductors, and other magnetic components to complete power exchange. Therefore, it is of small size, low cost, and high efficiency. ③ The fault current limiting is realized by the original topology without increasing the complexity of DCPFC structure, which can reduce the interruption current of the DCCB. After limiting the fault current, the bypass protection strategy is used to prevent capacitor overvoltage.

The rest of this paper is organized as follows. In Section II, the operation principle is analyzed. In Section III, the hierarchical power balance mechanism is studied, including the overall power balance and internal power balance. Then, the control strategy of power flow distribution and fault current limiting is presented in Section IV. Subsequently, the above analysis is verified by the simulation data and experimental results in Section V. In Section Ⅵ, MM-DCFPC is compared with several typical DCPFCs. Finally, conclusion is made in Section Ⅶ to summarize the findings and results.

II. Operation Principle

A. Topology of MM-DCPFC

The MM-DCPFC with m terminals is shown in Fig. 1(a), including m arms $(A 1, A 2, \dots, A m)$ with the same structure. It can be installed at one of the terminals ( $p_{1}$ , $p_{2}$ , or $p_{3}$ ) in the DC grid to redistribute the terminal current I₁ among $m - 1$ branches $(I_{l, 1}, I_{l, 2}, \dots, I_{l, m - 1})$ to make them meet expectations. The topology of the arm is shown in Fig. 1(b). Ignoring the small arm resistance, each arm is composed of N cascaded SMs and the arm inductance L_e. The SM contains a full-bridge module and two thyristors as shown in Fig. 1(c). Since each full-bridge can output $U_{C}$ , $- U_{C}$ , and 0 voltage levels, the peak value of the voltage output by N cascaded SMs is ±NU_C. Each arm can be equivalent to a controllable voltage source, and its output voltage u_x $(x = A 1, A 2, \dots, A m)$ can be controlled by adjusting the coefficient n_x:

u_{x} = n_{x} N U_{C} - 1 \leq n_{x} \leq 1

(1)

Fig. 1 Topology of MM-DCPFC. (a) Structure of m-terminal MM-DCPFC. (b) Structure of arm. (c) Structure of SM.

In order to meet the needs of power flow control under normal conditions and current limitation under fault conditions, MM-DCPCF has two operation modes: power flow control mode and fault current limiting mode. The thyristors in SMs will only be triggered in fault current limiting mode.

B. Power Flow Control Mode

In order to facilitate the analysis, a simple three-terminal MM-DCPFC is taken as an example to illustrate its operation principle. In the three-terminal DC grid shown in Fig. 2(a), to regulate the current I₁₂ and I₁₃, MM-DCPFC is installed at terminal 1, where U₁, U₂, and U₃ are the terminal voltages; I₁, I₂, and I₃ are the terminal currents; I₁₂, I₁₃, and I₂₃ are the line currents; and $u_{A 1}$ , $u_{A 2}$ , u_A3and i_A1, $i_{A 2}$ , i_A3 are the arm voltages and arm currents of A1, A2, and A3, respectively. The equivalent circuit of MM-DCPFC in power flow control mode is shown in Fig. 2(b), where the line impedance $Z_{y} = R_{y} + j L_{y}$ ( $y =$ 12, 13, 23) is mainly determined by the length of the lines.

Fig. 2 Three-terminal MM-DCPFC. (a) Three-terminal DC grid with MM-DCPFC. (b) Equivalent model of MM-DCPFC in power flow control mode. (c) DC loop equivalent circuit. (d) AC loop equivalent circuit.

In order to ensure the normal operation of MM-DCPFC in power flow control mode, the following two functional requirements need to be met: ① insert positive and negative DC voltages into the two transmission lines to regulate the power flow; ② complete power exchange internally to ensure its own power balance. Therefore, the output voltages of A1 and A3 contain both DC and AC components, where the DC voltage component is used to realize the first function, and the AC voltage component is used to achieve the power exchange between the two arms and realize the second function. In addition, the arm A2, which is not connected in series to any line, only outputs DC voltage and flows through AC circulating current. The equivalent circuit model can be obtained by decoupling AC and DC components in MM-DCPFC, as shown in Fig. 2(c) and (d), where ${\bar{u}}_{A 1}$ and ${\bar{u}}_{A 3}$ are the DC voltages of A1 and A3, respectively; ${\bar{i}}_{A 1}$ and ${\bar{i}}_{A 3}$ are the DC currents of A1 and A3, respectively; ${\tilde{u}}_{A 1}$ and ${\tilde{u}}_{A 3}$ are the AC voltages of A1 and A3, respectively; and ${\tilde{i}}_{A 1}$ and ${\tilde{i}}_{A 3}$ are the AC currents of A1 and A3, respectively.

According to the Kirchhoff’s voltage law and Fig. 2(c), we can obtain (2), which proves that the distribution of I₁ between the two branches can be changed by adjusting the DC components of u_A1 and u_A3.

\{\begin{array}{l} I_{12} = \frac{U_{1} - U_{2} - {\bar{u}}_{A 1}}{R_{12}} \\ I_{13} = \frac{U_{1} - U_{3} - {\bar{u}}_{A 3}}{R_{13}} \\ I_{23} = \frac{U_{2} - U_{3}}{R_{23}} \end{array}

(2)

According to the Kirchhoff’s current law and Fig. 2(c), we can obtain (3). It can be observed from (3) that if the terminal current I₁ is fixed, only one of I₁₂ and I₁₃ is fully controllable. Therefore, one degree of freedom is required to adjust the current of the two branches, and there is an extra degree of freedom among the adjustable quantities ${\bar{u}}_{A 1}$ and ${\bar{u}}_{A 2}$ in (2) that can be used to meet the external power balance.

\{\begin{array}{l} I_{1} = I_{12} + I_{13} \\ I_{12} = {\bar{i}}_{A 1} \\ I_{13} = {\bar{i}}_{A 3} \end{array}

(3)

According to Fig. 2(d), we can obtain (4), where $X = j ω L_{e}$ . It can be observed from (4) that the internal circulating AC current i_cir can be controlled by adjusting the AC voltage components of A1 and A3.

\{\begin{array}{l} {\tilde{i}}_{A 1} = i_{c i r} \\ {\tilde{i}}_{A 2} = i_{c i r} \\ {\tilde{i}}_{A 3} = - i_{c i r} \\ 3 X i_{c i r} = {\tilde{u}}_{A 1} - {\tilde{u}}_{A 3} \end{array}

(4)

C. Fault Current Limiting Mode

A single-pole grounding fault is assumed to occur on line 12 near terminal 2. The transient characteristics, current limiting mechanism, and self-protection scheme of MM-DCPFC are analyzed. As shown in Fig. 3(a), there are two paths to inject short-circuit current to the fault point: l₁₂, and l₁₃-l₂₃. Since arms A1 and A3 are respectively connected in series in two branches, the fault current of l₁₂ is limited by A1, while the fault current of the other path is suppressed by A3. The action sequence of A1 is as follows, and A3 is the same.

Fig. 3 Fault current limiting mode. (a) Flow path of fault current. (b) Fault current limiting stage. (c) Bypass protection stage.

1) Fault current limiting stage: after MM-DCPFC receives the fault command, all insulated gate bipolar transistors (IGBTs) will be blocked immediately to make each SM in an uncontrolled rectification state. The capacitor at the DC side is charged by the fault current through freewheeling diodes, and the reverse voltage is inserted in the l₁₂ to limit the fault current as shown in Fig. 3(b). Note that in Fig. 3, the dashed red line indicates the current flow path.

2) Bypass protection stage: in order to ensure the safety of the capacitor, once the capacitor voltage reaches the upper limit, the thyristors in parallel at the output end of the SM will be forced to conduct for commutation, so as to realize the self-protection function as shown in Fig. 3(c).

Since the current limiting function fails after the capacitor is bypassed, it is the effective current limiting time of MM-DCPFC from the fault detection to the bypass protection. The transient model of this stage is established, as shown in Fig. 4, where R_f and L_f are the total equivalent resistance and inductance of the fault circuit, respectively.

Fig. 4 Equivalent model of fault current limiting stage. (a) Equivalent model without fault current limiting. (b) Equivalent model with fault current limiting.

Figure 4(a) shows the equivalent circuit without current limiting, which satisfies:

- U_{1} + R_{f} i_{12} + L_{f} \frac{d i_{12}}{d t} = 0

(5)

If the steady-state line current is I₀, the fault current is calculated as:

i_{12} = \frac{U_{1}}{R_{f}} (1 - e^{- \frac{R_{f} t}{L_{f}}}) + I_{0} e^{- \frac{R_{f} t}{L_{f}}}

(6)

The equivalent circuit with current limiting is shown in Fig. 4(b).

- U_{1} + u_{A 1} + R_{f} i_{12} + L_{f} \frac{d i_{12}}{d t} = 0

(7)

u_{A 1} = u_{C} + L_{e} \frac{C_{1}}{N_{A 1}} \frac{d^{2} u_{C}}{d t}

(8)

where C₁ is the capacitance of the SM, and since the capacitors of the N_A1 SMs are connected in series, the capacitance becomes C₁/N_A1; and u_C is the capacitor voltage.

If a short-circuit fault occurs at t₀ and the initial capacitor voltage is U₀, u_C at t₁ can be expressed as:

u_{C} = \{\begin{array}{l} U_{0} + \frac{N_{A 1}}{C_{1}} \int_{t_{0}}^{t_{1}} i_{12}^{'} (t) d t & u_{C} \leq U_{l i m} \\ U_{l i m} & u_{C} > U_{l i m} \end{array}

(9)

where U_lim is the upper limit of capacitor voltage.

The fault current $i_{12}^{'}$ is calculated from (7):

i_{12}^{'} = \frac{U_{1} - u_{A 1}}{R_{f}} (1 - e^{- \frac{R_{f} t}{L_{f}}}) + I_{0} e^{- \frac{R_{f} t}{L_{f}}}

(10)

It can be observed from (6) and (10) that MM-DCPFC can reduce the line voltage from U₁ to $U_{1} - u_{A 1}$ by inserting a reverse voltage, and the current limiting capacity can be obtained by:

\frac{I_{L} - I_{L}^{'}}{I_{L}} = \frac{\frac{u_{A 1} (Δ t)}{R_{f}} (1 - e^{- \frac{R_{f} Δ t}{L_{f}}})}{\frac{U_{1}}{R_{f}} (1 - e^{- \frac{R_{f} Δ t}{L_{f}}}) + I_{0} e^{- \frac{R_{f} Δ t}{L_{f}}}}

(11)

where $Δ t$ is the time delay from fault occurrence to interruption; $I_{L}$ and $I_{L}^{'}$ are the fault currents at $Δ t$ in the DC system without and with current-limiting capability, respectively; and $u_{A 1} (Δ t)$ is the arm voltage of A1 at $Δ t$ .

Due to the small arm inductance in (8), it can be considered that all the current limiting capabilities are provided by the capacitor voltage. Moreover, compared with the fault current component, the steady-state component I₀ is very small and can be ignored. Therefore, when u_A1 and u_C are regarded as equal and I₀ is not considered, the current limiting capacity in (10) can be approximately expressed as:

\frac{I_{L} - I_{L}^{'}}{I_{L}} = \frac{u_{C} (Δ t)}{U_{1}}

(12)

where $u_{C} (Δ t)$ is the capacitor voltage at $Δ t$ .

Two factors affecting the current limiting capacity can be concluded: the capacitance value affects the rise rate of fault current, and the upper limit of capacitor voltage affects the current limiting time. The smaller the capacitance is, the faster the capacitor voltage rises in finite time, and the larger $u_{C} (Δ t)$ is. The larger the capacitor voltage limit is, the longer the effective current limiting time is. Therefore, the current limiting capacity of MM-DCPFC can be improved by appropriately reducing the capacitance and increasing the capacitor voltage limit. In addition, the most effective method is to increase the number of SMs in the arm, but the cost will increase. It is necessary to consider the cost and current limiting ability comprehensively and choose a better scheme in the actual application.

When U_lim of the capacitor is determined, the maximum possible current limiting capacity is also determined, as shown in (13). The premise of reaching this maximum is that the capacitor voltage of SMs just reaches U_lim at $Δ t$ . The capacitance value meeting this requirement can be calculated as follows. According to (6)-(8), the analytical expression $u_{C} (t)$ of u_C relative to t can be obtained. When the interruption time $Δ t$ of DCCB is known, $u_{C} (Δ t) = U_{l i m}$ can be solved to obtain the capacitance value with the maximum current limiting capacity.

{(\frac{I_{L} - I_{L}^{'}}{I_{L}})}_{m a x} = \frac{N U_{l i m}}{U_{1}}

(13)

When a single-pole grounding fault occurs, there is a case that does not cause a large fault current, i.e., the DC system is grounded through a large impedance, which can effectively limit the fault current. At this time, the fault current limiting stage can be skipped, and the MM-DCPFC is directly bypassed. In addition to line-to-ground faults, a line-to-line fault is a rare event, but the impact is catastrophic and also needs to be considered. When the DC system is in bipolar mode, both the positive and negative poles need to be installed with MM-DCPFC, and can be used to limit the fault current. Therefore, although the line-to-line fault is more serious, the current limiting capacity of MM-DCPFC is also greater.

III. Hierarchical Power Balance Mechanism

The power of A1 and A3 is shown in (14). The external and internal power balance is achieved by the following two power exchange mechanisms: ① the overall net power balance is realized by exchanging DC power between arms (A1 and A3) and the DC system; ② the internal power balance is realized by transferring average AC power between A1 and A3.

\{\begin{array}{l} P_{A 1} = {\bar{P}}_{A 1} + {\tilde{P}}_{A 1} \\ P_{A 3} = {\bar{P}}_{A 3} + {\tilde{P}}_{A 3} \end{array}

(14)

where ${\bar{P}}_{A 1}$ and ${\bar{P}}_{A 3}$ are the DC power of A1 and A3, respectively; and ${\tilde{P}}_{A 1}$ and ${\tilde{P}}_{A 3}$ are the average AC power of A1 and A3, respectively.

A. External Power Balance

MM-DCPFC has no power loss under ideal conditions, i.e., the DC power exchanged between A1 and DC system is balanced with that exchanged between A3 and DC system:

{\bar{P}}_{A 1} + {\bar{P}}_{A 3} = 0

(15)

According to (15), we can obtain:

{\bar{u}}_{A 1} I_{12} = - {\bar{u}}_{A 3} I_{13}

(16)

Although MM-DCPFC has no loss under ideal conditions, in actual operation, when affected by power devices and equipment losses, MM-DCPFC needs to properly absorb the power from the outside to achieve its overall power balance:

{\bar{P}}_{A 1} + {\bar{P}}_{A 3} = P_{l o s s}

(17)

Since DC currents are regulated quantities, the overall power balance can only be realized by adjusting the DC voltage of arms. When $Δ u_{d c}$ is added to ${\bar{u}}_{A 1}$ and ${\bar{u}}_{A 2}$ to compensate the internal loss, the compensated power loss is obtained as:

P_{l o s s} = Δ u_{d c} (I_{12} + I_{13}) = Δ u_{d c} I_{1}

(18)

For three-terminal MM-DCPFC, ${\bar{u}}_{A 1}$ and ${\bar{u}}_{A 2}$ provide two degrees of freedom in order to satisfy (2) and (16), i.e., power flow control and external power balance. It can be inferred that for m-terminal MM-DCPFC, the DC voltage component of arms should provide $m - 1$ degrees of freedom to realize power flow control and overall power balance, and the extra arm such as A2 in three-terminal MM-DCPFC exists as a balancing arm, and its main functions are providing a pathway for circulating AC current i_cir. The DC voltage of A2 can also be used to compensate the DC voltage difference between A1 and A3 to eliminate the circulating DC current inside the MM-DCPFC. Therefore, u_A2 needs to satisfy:

{\bar{u}}_{A 1} + u_{A 2} - {\bar{u}}_{A 3} = 0

(19)

It can be observed from the above analysis that A2 neither needs to output AC voltage nor limits the fault current. Therefore, the number of SMs of A2 can be reduced, and even can be replaced by a non-polar capacitor.

B. Internal Power Balance

In order to ensure the internal power balance of MM-DCPFC, the power of the A1 and A3 needs to meet: ① the DC power of one arm is balanced with its own average AC power; ② the average AC power of one arm is balanced with that of the other, that is:

\{\begin{array}{l} {\bar{P}}_{A 1} = - {\tilde{P}}_{A 1} \\ {\bar{P}}_{A 3} = - {\tilde{P}}_{A 3} \\ {\tilde{P}}_{A 1} = - {\tilde{P}}_{A 3} \end{array}

(20)

The two arms transfer the power in the form of average AC power, so it is necessary to modulate the AC voltage and circulating AC current to meet the needs of internal power balance. The AC voltage components of A1 and A3 can be decomposed into u_x and u_y:

\{\begin{array}{l} {\tilde{u}}_{A 1} = u_{x} + u_{y} \\ {\tilde{u}}_{A 3} = u_{x} - u_{y} \end{array}

(21)

where u_x is used to generate average AC power and has the same phase as i_cir; and u_y is 90° ahead of the phase of i_cir to compensate reactive power and generate AC circulating current.

Equation (22) can be derived from (16) and (20).

\begin{matrix} \{\begin{array}{l} \frac{1}{2} {\hat{u}}_{x} {\hat{i}}_{c i r} = {\bar{u}}_{A 1} {\bar{i}}_{A 1} \\ {\bar{u}}_{A 1} {\bar{i}}_{A 1} = - {\bar{u}}_{A 3} {\bar{i}}_{A 3} \end{array} \end{matrix}

(22)

where ${\hat{u}}_{x}$ and ${\hat{i}}_{c i r}$ are the amplitudes of u_x and i_cir, respectively.

One degree of freedom is needed to satisfy (22) and realize internal power balance, and an extra degree of freedom among the two adjustable variables ${\hat{u}}_{x}$ and ${\hat{i}}_{c i r}$ can be used for optimization. Since A1 and A3 will inevitably insert AC voltage in the lines and cause current ripple, ${\hat{u}}_{x}$ can be reduced as much as possible, which needs to increase ${\hat{i}}_{c i r}$ , and then increase a part of loss to reduce the ripple. In addition to the optimization inside the device, series inductors can also be used to reduce the current ripple.

Equation (20) is based on the ideal condition that A2 has no loss. Under actual conditions, in order to maintain the power balance of A2, an AC voltage ∆u_ac is subtracted and added to the voltage of A1 and A3, respectively, and the compensated loss of A2 is as follows:

P_{l o s s}^{A 2} = Δ {\hat{u}}_{a c} {\hat{i}}_{c i r}

(23)

where $Δ {\hat{u}}_{a c}$ is the amplitude of $Δ u_{a c}$ .

Based on the above analysis, the arm voltages u_A1, u_A2, u_A3 and arm currents i_A1, i_A2, i_A3 can be expressed as:

\{\begin{array}{l} u_{A 1} = {\bar{u}}_{A 1} + {\tilde{u}}_{A 1} = U_{1} - U_{2} - I_{12} R_{12} + Δ u_{d c} + u_{x} + u_{y} - Δ u_{a c} \\ u_{A 2} = {\bar{u}}_{A 3} - {\bar{u}}_{A 1} \\ u_{A 3} = {\bar{u}}_{A 3} + {\tilde{u}}_{A 3} = U_{1} - U_{3} - I_{13} R_{13} + Δ u_{d c} + u_{x} - u_{y} + Δ u_{a c} \end{array}

(24)

\{\begin{array}{l} i_{A 1} = {\bar{i}}_{A 1} + {\tilde{i}}_{A 1} = I_{12} + i_{c i r} \\ i_{A 2} = i_{c i r} \\ i_{A 3} = {\bar{i}}_{A 3} + {\tilde{i}}_{A 3} = I_{13} - i_{c i r} \end{array}

(25)

The electrical stress is also a major concern in actual design, which will affect the cost and volume of hardware. Therefore, the voltage and current stresses for key power electronic devices are listed in Table I, where I_peak is the peak value of fault current.

TABLE I Voltage and Current Stresses of Key Power Electronic Devices

Device	Current stress	Voltage stress
IGBT of A1 and A3	$\sqrt[]{I_{1}^{2} + {\hat{i}}_{c i r}^{2} / 2}$	U_lim
IGBT of A2	${\hat{i}}_{c i r} / \sqrt[]{2}$	U_lim
Diode	I_peak	U_lim/2
Thyristor	I_peak	U_lim

IV. Control Strategy of Power Flow Distribution and Fault Current Limiting

The control system of MM-DCPFC is divided into power flow control mode and fault current limiting mode. In the power flow control mode, there are mainly current distribution control and power balance control, as shown in Fig. 5(a), where $I_{12}^{r e f}$ and $i_{c i r}^{r e f}$ are the reference values of line current I₁₂ and circulating AC current i_cir, respectively; $U_{C}^{A 1} (i)$ , $U_{C}^{A 2} (j)$ , and $U_{C}^{A 3} (k)$ are the SM capacitor voltages of A1, A2, and A3, respectively; $U_{C, r e f}^{A 1}$ , $U_{C, r e f}^{A 2}$ , and $U_{C, r e f}^{A 3}$ are the capacitor voltage reference values of A1, A2, and A3, respectively; $Δ u_{C}^{A 1} (i)$ , $Δ u_{C}^{A 2} (j)$ , and $Δ u_{C}^{A 3} (k)$ are the modulation commands of internal capacitor voltage sharing of A1, A2, and A3, respectively; and u_A1(i), u_A2(j), and u_A3(k) are voltage modulation commands of SMs of A1, A2, and A3, which are converted into switching signals by carrier-phase-shifted pulse width modulation (PWM) method [

20].

Fig. 5 Control block diagram of MM-DCPFC. (a) Overall control. (b) Current distribution control. (c) Power balance control. (d) A1 and A3 power balance control. (e) A2 power balance control. (f) SM power balance control.

A. Current Distribution Control

The current distribution control includes open-loop feedforward control and closed-loop feedback control, as shown in Fig. 5(b). According to (2), the DC component of arm voltage mainly depends on the current distribution and the length of the lines. Given the reference values of I₁₂ and the terminal current I₁, the initial DC voltage values of A1 and A3 can be calculated according to (2). In order to improve the accuracy and dynamic performances, a closed-loop feedback control is added, and the output command of PI controller is combined with the above initial value to output DC voltage command.

B. Power Balance Control

The power balance of MM-DCPFC is controlled at three levels: overall power balance, arm power balance, and SM power balance.

Figure 5(c) shows the power balance control, where $U_{C, r e f}^{s u m}$ is the reference value of the sum of all capacitor voltages, and $U_{C, r e f}^{s u m} = U_{C, r e f}^{A 1} + U_{C, r e f}^{A 2} + U_{C, r e f}^{A 3}$ . According to Section III-A, $Δ u_{d c}$ is added to the DC voltage of A1 and A3 to compensate for losses and thus ensure overall power balance.

The control block diagram of arm power balance is shown in Fig. 5(d), where PR stands for proportional-resonant. i_cir is modulated by adding and subtracting AC voltage u_y respectively at the voltage of A1 and A3. Given the reference value of i_cir, PR controller is used to generate the command u_y to make i_cir track the reference value. According to (22), AC voltages of the arms need to be modulated to meet the power balance requirements. PI controller is used to output the command of AC voltage amplitude of the arm, and then the sinusoidal command u_x is obtained. Furthermore, according to Section III-B, $Δ u_{a c}$ is subtracted and added to the AC voltage of A1 and A3 respectively to realize the power balance of A2, as shown in Fig. 5(e).

The above control strategy ensures the power balance of the whole MM-DCPFC and the arms. In addition, the capacitor voltage sharing control is needed to ensure the power balance of each SM. Figure 5(f) shows that the control block diagrams of A1, A2, and A3 are the same. The control strategy is as follows. The average value of all capacitor voltages in one arm is calculated. Each capacitor voltage is made to track this average value. The commands $Δ u_{C}^{A 1} (i)$ $(i = 1, 2, \dots, N_{A 1})$ output by the PI controller cause a small change in the modulation wave of each SM to ensure the balance of the capacitor voltage.

C. Fault Current Limiting Control

Whether MM-DCPFC can limit the current in the entire fault process can be divided into the following two situations.

1) If the capacitor voltage reaches the upper limit U_lim before the fault is cleared, MM-DCPFC will first limit the fault current, and then it will be bypassed when $U_{C} = U_{l i m}$ , and the current limiting function will also fail. Since the DCCB has not been activated at this time, the current will continue to rise at a large rate until the fault is cleared. The curve of short-circuit current is shown in Fig. 6(a).

Fig. 6 Fault current limiting mode control. (a) Current curve of situation 1. (b) Current curve of situation 2. (c) Action sequence of MM-DCPFC in fault current limiting mode.

2) If the capacitor voltage does not reach U_lim before the fault is cleared, the current limiting function can be exerted during the entire short-circuit fault process, as shown in Fig. 6(b).

The action sequence of MM-DCPFC in fault current limiting mode can be obtained based on the above two situations, as shown in Fig. 6(c). Since the second situation is generally expected, under a certain operation condition, MM-DCPFC can limit the fault current during the entire fault process by selecting the capacitance and the upper limit of the capacitor voltage reasonably.

V. Simulation and Experimental Verification

The simulation model of three-terminal DC system with MM-DCPFC in Fig. 2(a) is built in PLECS, where terminal 1 operates in constant voltage control mode and U₁ = 200 kV, while terminal 2 and terminal 3 operate in constant power control mode and P₂ = -81 MW, P₃ = -157 MW. The main parameters of the transmission lines are shown in Table II [

11], [21], and the parameters of three-terminal MM-DCPFC are shown in Table III.

TABLE II Parameters of Transmission Lines

DC line	Distance (km)	Resistance (Ω)	Inductance (H)	Capacitance(μF)
Line 12	400	4	0.16	480
Line 13	300	3	0.12	360
Line 23	300	3	0.12	360

TABLE III Parameters of Three-terminal MM-DCPFC

Parameter	Value
C₁	3 mF
N_A1	10
N_A2	1
N_A3	10
$L_{e}$	1 mH
$i_{c i r}^{r e f}$	200 A

A. Start-up and Power Flow Control

The power flow control mode of MM-DCPFC consists of two basic stages: start-up stage and normal operating stage. The control objective of the start-up stage is to charge capacitors to the rated operating voltage. Thus, only the power balance mechanism is put into operation in this stage, while the current distribution mechanism does not work, and the control method is the same as that in Section IV-B. MM-DCPFC is started at $t = 0.2 s$ . As can be observed from Fig. 7(a), MM-DCPFC absorbs energy from the DC system during the rise of capacitor voltage, causing slight fluctuation of line current, and it will no longer affect line current when the capacitor voltage is stable.

Fig. 7 Simulation waveforms of start-up and power flow control. (a) Line currents. (b) Capacitor voltages of SMs. (c) Arm currents. (d) Arm voltages.

The power flow control starts at 1 s, and the given value of I₁₂ is 0.6 kA. Before starting the power flow control, the line current is $I_{1} = 1.20$ kA, $I_{12} = 0.49$ kA, $I_{13} = 0.71$ kA. After starting the power flow control, the line current is regulated according to the given value and stabilized again. At this time, $I_{12} = 0.6$ kA, $I_{13} = 0.6$ kA, as shown in Fig. 7(a). It can be observed from Fig. 7(b) that the capacitor voltage of SMs of A1 and A3 can be stabilized at 400 V, and that of A2 can be stabilized at 900 V.

B. Fault Current Limiting

At $t = 3$ s, a short-circuit fault shown in Fig. 3(a) occurs. In the absence of any current limiting measures, the line current rises rapidly, far exceeding the rated current, and continues to rise to 3.96 kA before the fault is cleared. In the system with fault current limiting capacity, the fault is detected at 0.2 ms after occurrence and cleared at 3.5 ms. At this time, $I_{12} = 3.43$ kA, which is reduced by 13.31% compared with no current limiting, as shown in Fig. 8(a). It can be observed from Fig. 8(b) that the capacitor voltage in SMs rises to the set protection value (5 kV) at 5 ms after the fault occurs, and then it is bypassed. After that, in order to protect the power electronic modules, it is necessary to discharge the capacitor to a safe voltage level. Therefore, a large resistor controlled by a switch can be connected in parallel with the capacitor to consume its energy.

Fig. 8 Simulation waveforms of fault current limiting mode. (a) Line currents. (b) Capacitor voltages of SMs. (c) Comparison of current limiting capability with different capacitance values. (d) Comparison of effective current limiting time with different voltage limits.

In order to further study the current limiting characteristics, simulations are carried out for different capacitance values and different upper limits of capacitor voltage. When U_lim is set to be 5 kV, the current limiting capability corresponding to different capacitances is shown in Fig. 8(c). When the capacitance is set to be 5 mF, the effective current limit time corresponding to different U_lim is shown in Fig. 8(d). The simulation results are consistent with the theoretical analysis of Section II-C.

C. Four-terminal MM-DCPFC

In order to verify the scalability of MM-DCPFC, four-terminal power flow controller is simulated. The four-terminal MM-DCPFC is composed of four arms, i.e., $m = 4$ in Fig. 1, which can adjust the distribution of terminal currents in the three branches l₁, l₂, and l₃. The parameters of three branches connected to terminal 1 are shown in Table IV, and the SM capacitance and arm inductance of MM-DCPFC are the same as those in Table III. There is one SM in A2, while there are 10 SMs in A1, A3, and A4, and the simulation results are shown in the Fig. 9. The MM-DCPFC is started at $t = 0.2$ s, and capacitor voltages are established. At this time, $I_{12} = 0.34$ kA, $I_{12} = 0.43$ kA, $I_{13} = 0.43$ kA. The power flow control starts at 1 s, and the currents of lines are stable as $I_{12} = 0.5 k A$ , $I_{12} = 0.35 k A$ , $I_{13} = 0.35 k A$ , which is equal to the expected value as shown in Fig. 9(a). The capacitor voltages of A1, A3, and A4 can be stabilized at 500 V, while that of A2 can be stabilized at 1200 V, as shown in Fig. 9(b).

Fig. 9 Simulation waveforms of four-terminal MM-DCPFC. (a) Line currents. (b) Capacitor voltages of SMs.

TABLE Ⅳ Line Parameters of Four-terminal MM-DCPFC

DC line	Distance (km)	Resistance (Ω)	Inductance (H)	Capacitance(μF)
Line12	500	5	0.20	600
Line13	400	4	0.16	480
Line14	400	4	0.16	480

D. Experimental Validation

In order to verify the function and control method of MM-DCPFC, a small-scale experimental system shown in Fig. 10 is built in the laboratory, and the parameters of DC system are: $U_{1} = 300 V$ , $P_{2} = - 1 k W$ and $P_{3} = - 1 k W$ , $R_{12} = 3.6 Ω$ , $R_{13} = 5.4 Ω$ . In the MM-DCPFC prototype, there is one SM in A1 and A3, and A2 is replaced by capacitance as described in Section III-A, and the amplitude of AC circulating current is set to be 3 A.

Fig. 10 Picture of experimental system.

The reference values of I₁₂ and the capacitor voltage are 3 A and 30 V, respectively. In the initial state, MM-DCPFC is bypassed and the line currents are naturally distributed. Since the capacitor voltage is small, the capacitor voltage establishment and power flow regulation are carried out simultaneously after MM-DCPFC is put into operation. When the system reaches to be stable, the line current and the capacitor voltage are equal to their reference values as shown in Fig. 11(a) and Fig. 11(b). The current waveforms of A1 and A3 are shown in Fig. 11(c), where the DC components are equal to the line currents of 3 A and 4 A, respectively, and the amplitude of the AC component is 3 A. The output voltages of A1 and A3 are three-level waveforms as shown in Fig. 11(d).

Fig. 11 Simulation (left) and experimental (right) results of power flow control mode. (a) DC line current. (b) Capacitor voltage. (c) Arm current. (d) Arm voltage.

The experimental results under fault conditions are shown in Fig. 12, where $C_{1} = 500$ $μ F$ , and $U_{l i m} = 150$ V. Due to the low-voltage level of the system, with the increase of the capacitor voltage, the fault current not only increases slowly, but also begins to decrease. At 3.5 ms after the fault occurs, I₁₂ is 15.6 A in the system without fault current limiting function and 8.4 A in the system with fault current limiting function, and the current limiting capacity is 46.15%. At 5.04 ms after the fault, the capacitor voltage reaches 150 V and is bypassed. At this time, I₁₂ drops to 5.6 A. Since there is no DCCB, it will continue to rise as shown in Fig. 12(b). In practical applications, the fault current can be interrupted by DCCB within 3-5 ms [

22].

Fig. 12 Experimental results of fault current limiting mode. (a) I₁₂ without current limiting. (b) Capacitor voltage and I₁₂ with current limiting.

VI. Comparison with Other Typical IDCPFCs

Firstly, as a power flow control device, MM-DCPFC is compared with IDCPFCs, which are also of modular cascaded structures.

The modular IDCPFCs proposed in [

13] and [14] are composed of modular multi-level converters (MMCs) and an AC transformer. In contrast, MM-DCPFC applies a power exchange mechanism based on the circulating AC current without the need for the transformer, which is beneficial to reduce the volume and cost of DCPFC. In addition, although both of them are cascaded schemes, the number of power electronic devices of the three-phase converter used in [13] and [14] is three times that of this paper at the same voltage level of DC side. Even if MM-DCPFC adds an additional A3, the number of SMs of this arm is small.

The cascaded form of dual-H-bridge IDCPFC is proposed in [

15].

Bidirectional switches are added in [

15] to realize the isolation of the capacitor voltage, thereby ensuring that the currents of two lines are independent of each other. At the same voltage level, i.e., the number of SMs is N, the number of power electronic devices in [15] is 16N, of which 8N are used as isolation switches. For MM-DCPFC, if the number of SMs in A1 and A2 is N, and the number of SMs in A3 is n, the number of power electronic devices used for power flow control is

8 N + 4 n

(bypass thyristors do not participate in power flow regulation). Taking the simulation parameters as an example, where

N = 10

n = 1

, the scheme in [15] needs 160 IGBTs, while MM-DCPFC needs 84 IGBTs. Moreover, the voltage stress of the isolation switches in [15] increases with the number of SMs. Therefore, MM-DCPFC can not only save more than 45% of power electronic devices, but also has advantages in the voltage stress of the devices.

The power balance of IDCPFCs in [

15] and [16] can be achieved by their own power exchange mechanism instead of transformers. When realizing multi-line power flow regulation, the mechanism needs to install multiple IDCPFCs with the same structure. In contrast, MM-DCPFC provides a scheme of expanding the number of arms for multi-line regulation, which makes the advantages of MM-DCPFC continue to expand in the DC grid with complex structure.

In addition to the basic power flow control function, the current limiting function of MM-DCPFC indirectly reduces the cost of DCCBs. Without consideration of other current limiting devices, we compare the cost of circuit breaker when installing ordinary DCPFC (scheme 1) and MM-DCPC (scheme 2). Assuming that the DCCB is ABB’s hybrid DC breaker [

23], and the IGBT model is 5SNA1200G450300, with rated voltage of 4500 V and rated current of 1200 A. Under the simulation parameters in Section V, the DCCB needs to withstand the over-current and over-voltage when a fault occurs. There is no current limiting measure in scheme 1, so the DCCB needs to withstand the peak fault current of 3.96 kA and the system-level voltage of 200 kV, in which the voltage needs to retain 1.5 times of margin. Therefore, scheme 1 needs 67 IGBTs in series and 4 IGBTs in parallel. In order to ensure bidirectional controllability, a total of 536 IGBTs are needed. In scheme 2, the fault current can be limited by MM-DCPFC, so the DCCB needs to withstand the peak fault current of 3.43 kA and the system-level voltage of 200 kV. Considering the voltage margin and current bidirectionality, scheme 2 needs 402 IGBTs, of which 67 are connected in series and 3 are connected in parallel. Although MM-DCPFC adds 40 thyristors to protect itself, the overall number of power electronic devices is still reduced. In addition to cost saving, the reduction in the number of power electronic devices is accompanied by a reduction in gate drivers and monitoring and communication systems, thus reducing the overall power loss.

In summary, the comparison of several typical modular IDCPFCs is presented in Table V.

TABLE Ⅴ Comparison of Several Typical Modular IDCPFC

Scheme	Economy	Loss	Power flow regulation ability	Port scalability
IDCPFC in [13], [14]	1	1	5	4
IDCPFC in [15]	1	2	5	-
IDCPFC in [16]	3	3	5	-
MM-DCPFC	5	4	5	5

Note: 1 represents very bad; 2 represents poor; 3 represents moderate; 4 represents good; 5 represents very good; and “-” means that this function is not available.

VII. Conclusion

The MM-DCPFC proposed in this paper adopts a modular structure and has strong scalability. The power flow regulation between multiple lines can be realized by expanding the number of arms, and it can be applied to high-voltage scenarios by expanding the number of SMs. A hierarchical control method is proposed to achieve its own power balance. The simulation and experimental results verify the power flow control and power balance functions. In fault current limiting mode, MM-DCPFC can limit the rise of fault current before protecting itself. The simulation and experimental results show that MM-DCPFC can reduce the peak value of the fault current, and the current-limiting capability can be further improved by reducing the capacitance and increasing the withstand voltage value of the capacitor.

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